VM: Use constant pool also for leaf runtime calls on x64, arm, arm64 and mips.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 2660 matching lines @@
 void Assembler::Vdivqs(QRegister qd, QRegister qn, QRegister qm) {
   ASSERT(qd != QTMP);
   ASSERT(qn != QTMP);
   ASSERT(qm != QTMP);
 
   Vreciprocalqs(qd, qm);
   vmulqs(qd, qn, qd);
 }
 
 
-void Assembler::Branch(const ExternalLabel* label, Condition cond) {
-  LoadImmediate(IP, label->address(), cond);  // Address is never patched.
-  bx(IP, cond);
-}
-
-
 void Assembler::Branch(const StubEntry& stub_entry, Condition cond) {
   const ExternalLabel label(stub_entry.EntryPoint());
-  Branch(&label, cond);
+  LoadImmediate(IP, label.address(), cond);  // Address is never patched.

[rmacnak, 2015/08/26 23:55:24]

Shouldn't this be LoadExternalLabel? We still need to relocate it, no?

[Florian Schneider, 2015/08/27 08:27:19]

Yes, using LoadExternalLabel is necessary here and will work without any further
changes since this branch won't be patched.

[Florian Schneider, 2015/08/27 08:38:09]

Correction: Actually, it won't work right away, since this sequence is still
used in places where there is no constant pool loaded.
(FlowGraphCompiler::EmitFrameEntry)

+  bx(IP, cond);
 }
 
 
-void Assembler::BranchPatchable(const ExternalLabel* label) {
+void Assembler::BranchPatchable(const StubEntry& stub_entry) {
   // Use a fixed size code sequence, since a function prologue may be patched
   // with this branch sequence.
   // Contrarily to BranchLinkPatchable, BranchPatchable requires an instruction
   // cache flush upon patching.
-  LoadPatchableImmediate(IP, label->address());
+  const ExternalLabel label(stub_entry.EntryPoint());
+  LoadPatchableImmediate(IP, label.address());

[rmacnak, 2015/08/26 23:55:24]

Ditto

[Florian Schneider, 2015/08/27 08:27:19]

Yes, but not the purpose of this CL (see description): The instruction patterns
in the patching code need to change as well if I use LoadExternalLabel. I just
changed code generation for leaf runtime calls plus I just removed unused
variants of Branch/BranchLink here without changing the generated code.

   bx(IP);
 }
 
 
-void Assembler::BranchPatchable(const StubEntry& stub_entry) {
-  const ExternalLabel label(stub_entry.EntryPoint());
-  BranchPatchable(&label);
-}
-
-
 void Assembler::BranchLink(const ExternalLabel* label) {
   LoadImmediate(LR, label->address());  // Target address is never patched.
   blx(LR);  // Use blx instruction so that the return branch prediction works.
 }
 
 
-void Assembler::BranchLink(const StubEntry& stub_entry) {
-  const ExternalLabel label(stub_entry.EntryPoint());
-  BranchLink(&label);
-}
-
-
 void Assembler::BranchLink(const ExternalLabel* label, Patchability patchable) {
   // Make sure that class CallPattern is able to patch the label referred
   // to by this code sequence.
   // For added code robustness, use 'blx lr' in a patchable sequence and
   // use 'blx ip' in a non-patchable sequence (see other BranchLink flavors).
   const int32_t offset = ObjectPool::element_offset(
       object_pool_wrapper_.FindExternalLabel(label, patchable));
   LoadWordFromPoolOffset(LR, offset - kHeapObjectTag);
   blx(LR);  // Use blx instruction so that the return branch prediction works.
 }
 
 
 void Assembler::BranchLink(const StubEntry& stub_entry,
                            Patchability patchable) {
   const ExternalLabel label(stub_entry.EntryPoint());
   BranchLink(&label, patchable);
 }
 
 
-void Assembler::BranchLinkPatchable(const ExternalLabel* label) {
-  BranchLink(label, kPatchable);
-}
-
-
 void Assembler::BranchLinkPatchable(const StubEntry& stub_entry) {
   const ExternalLabel label(stub_entry.EntryPoint());
-  BranchLinkPatchable(&label);
+  BranchLink(&label, kPatchable);
 }
 
 
 void Assembler::BranchLinkOffset(Register base, int32_t offset) {
   ASSERT(base != PC);
   ASSERT(base != IP);
   LoadFromOffset(kWord, IP, base, offset);
   blx(IP);  // Use blx instruction so that the return branch prediction works.
 }
 
@@ skipping 491 matching lines @@
   // Reserve space for arguments and align frame before entering
   // the C++ world.
   AddImmediate(SP, -frame_space);
   if (OS::ActivationFrameAlignment() > 1) {
     bic(SP, SP, Operand(OS::ActivationFrameAlignment() - 1));
   }
 }
 
 
 void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
-  // Preserve volatile CPU registers.
-  EnterFrame(kDartVolatileCpuRegs | (1 << FP), 0);
+  // Preserve volatile CPU registers and PP.
+  EnterFrame(kDartVolatileCpuRegs | (1 << PP) | (1 << FP), 0);
+  COMPILE_ASSERT((kDartVolatileCpuRegs & (1 << PP)) == 0);
 
   // Preserve all volatile FPU registers.
   if (TargetCPUFeatures::vfp_supported()) {
     DRegister firstv = EvenDRegisterOf(kDartFirstVolatileFpuReg);
     DRegister lastv = OddDRegisterOf(kDartLastVolatileFpuReg);
     if ((lastv - firstv + 1) >= 16) {
       DRegister mid = static_cast<DRegister>(firstv + 16);
       vstmd(DB_W, SP, mid, lastv - mid + 1);
       vstmd(DB_W, SP, firstv, 16);
     } else {
       vstmd(DB_W, SP, firstv, lastv - firstv + 1);
     }
   }
 
+  LoadPoolPointer();
+
   ReserveAlignedFrameSpace(frame_space);
 }
 
 
 void Assembler::LeaveCallRuntimeFrame() {
   // SP might have been modified to reserve space for arguments
   // and ensure proper alignment of the stack frame.
   // We need to restore it before restoring registers.
   const intptr_t kPushedFpuRegisterSize =
       TargetCPUFeatures::vfp_supported() ?
       kDartVolatileFpuRegCount * kFpuRegisterSize : 0;
 
-  // We subtract one from the volatile cpu register count because, even though
-  // LR is volatile, it is pushed ahead of FP.
+  COMPILE_ASSERT(PP < FP);
+  COMPILE_ASSERT((kDartVolatileCpuRegs & (1 << PP)) == 0);
+  // kVolatileCpuRegCount +1 for PP, -1 because even though LR is volatile,
+  // it is pushed ahead of FP.
   const intptr_t kPushedRegistersSize =
-      (kDartVolatileCpuRegCount - 1) * kWordSize + kPushedFpuRegisterSize;
+      kDartVolatileCpuRegCount * kWordSize + kPushedFpuRegisterSize;
   AddImmediate(SP, FP, -kPushedRegistersSize);
 
   // Restore all volatile FPU registers.
   if (TargetCPUFeatures::vfp_supported()) {
     DRegister firstv = EvenDRegisterOf(kDartFirstVolatileFpuReg);
     DRegister lastv = OddDRegisterOf(kDartLastVolatileFpuReg);
     if ((lastv - firstv + 1) >= 16) {
       DRegister mid = static_cast<DRegister>(firstv + 16);
       vldmd(IA_W, SP, firstv, 16);
       vldmd(IA_W, SP, mid, lastv - mid + 1);
     } else {
       vldmd(IA_W, SP, firstv, lastv - firstv + 1);
     }
   }
 
   // Restore volatile CPU registers.
-  LeaveFrame(kDartVolatileCpuRegs | (1 << FP));
+  LeaveFrame(kDartVolatileCpuRegs | (1 << PP) | (1 << FP));
 }
 
 
 void Assembler::CallRuntime(const RuntimeEntry& entry,
                             intptr_t argument_count) {
   entry.Call(this, argument_count);
 }
 
 
 void Assembler::EnterDartFrame(intptr_t frame_size) {
@@ skipping 354 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM