Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(744)

Side by Side Diff: tests_lit/assembler/x86/jump_encodings.ll

Issue 1312433004: Weight variables by their number of uses for register allocation. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 3 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
OLDNEW
1 ; Tests various aspects of x86 branch encodings (near vs far, 1 ; Tests various aspects of x86 branch encodings (near vs far,
2 ; forward vs backward, using CFG labels, or local labels). 2 ; forward vs backward, using CFG labels, or local labels).
3 3
4 ; Use -ffunction-sections so that the offsets reset for each function. 4 ; Use -ffunction-sections so that the offsets reset for each function.
5 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \ 5 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \
6 ; RUN: -ffunction-sections | FileCheck %s 6 ; RUN: -ffunction-sections | FileCheck %s
7 7
8 ; Use atomic ops as filler, which shouldn't get optimized out. 8 ; Use atomic ops as filler, which shouldn't get optimized out.
9 declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32) 9 declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32)
10 declare i32 @llvm.nacl.atomic.load.i32(i32*, i32) 10 declare i32 @llvm.nacl.atomic.load.i32(i32*, i32)
(...skipping 151 matching lines...) Expand 10 before | Expand all | Expand 10 after
162 br label %next 162 br label %next
163 next: 163 next:
164 %ptr = inttoptr i32 %iptr to i32* 164 %ptr = inttoptr i32 %iptr to i32*
165 call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6) 165 call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
166 br label %next2 166 br label %next2
167 next2: 167 next2:
168 %cmp = icmp ult i64 %val64, 0 168 %cmp = icmp ult i64 %val64, 0
169 br i1 %cmp, label %next, label %next2 169 br i1 %cmp, label %next, label %next2
170 } 170 }
171 ; CHECK-LABEL: test_local_forward_then_back 171 ; CHECK-LABEL: test_local_forward_then_back
172 ; CHECK: 14: {{.*}} mov DWORD PTR 172 ; CHECK: {{.*}} mov DWORD PTR
173 ; CHECK-NEXT: 16: {{.*}} mfence 173 ; CHECK-NEXT: {{.*}} mfence
174 ; CHECK-NEXT: 19: {{.*}} mov DWORD PTR {{.*}},0x1 174 ; CHECK-NEXT: 16: {{.*}} mov {{.*}},0x1
175 ; CHECK-NEXT: 20: {{.*}} cmp 175 ; CHECK-NEXT: {{.*}} cmp
176 ; CHECK-NEXT: 23: {{.*}} jb 33 176 ; CHECK-NEXT: {{.*}} jb
177 ; CHECK: 37: {{.*}} jne 14 177 ; CHECK: {{.*}} jne
178 ; CHECK: 39: {{.*}} jmp 19 178 ; CHECK: {{.*}} jmp 16
179 179
180 180
181 ; Test that backward local branches also work and are small. 181 ; Test that backward local branches also work and are small.
182 ; Some of the atomic instructions use a cmpxchg loop. 182 ; Some of the atomic instructions use a cmpxchg loop.
183 define void @test_local_backward(i64 %val64, i32 %iptr, i32 %val) { 183 define void @test_local_backward(i64 %val64, i32 %iptr, i32 %val) {
184 entry: 184 entry:
185 br label %next 185 br label %next
186 next: 186 next:
187 %ptr = inttoptr i32 %iptr to i32* 187 %ptr = inttoptr i32 %iptr to i32*
188 %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 5, i32* %ptr, i32 %val, i32 6) 188 %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 5, i32* %ptr, i32 %val, i32 6)
189 br label %next2 189 br label %next2
190 next2: 190 next2:
191 %success = icmp eq i32 1, %a 191 %success = icmp eq i32 1, %a
192 br i1 %success, label %next, label %next2 192 br i1 %success, label %next, label %next2
193 } 193 }
194 ; CHECK-LABEL: test_local_backward 194 ; CHECK-LABEL: test_local_backward
195 ; CHECK: 9: {{.*}} mov {{.*}},DWORD 195 ; CHECK: 9: {{.*}} mov {{.*}},DWORD
196 ; CHECK: b: {{.*}} mov 196 ; CHECK: b: {{.*}} mov
197 ; CHECK-NEXT: d: {{.*}} xor 197 ; CHECK-NEXT: d: {{.*}} xor
198 ; CHECK-NEXT: f: {{.*}} lock cmpxchg 198 ; CHECK-NEXT: f: {{.*}} lock cmpxchg
199 ; CHECK-NEXT: 13: 75 f6 jne b 199 ; CHECK-NEXT: 13: 75 f6 jne b
200 ; CHECK: 1c: 74 eb je 9 200 ; CHECK: 1c: 74 eb je 9
OLDNEW
« no previous file with comments | « src/IceTargetLoweringX86BaseImpl.h ('k') | tests_lit/assembler/x86/opcode_register_encodings.ll » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698