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Side by Side Diff: tests_lit/llvm2ice_tests/nacl-atomic-cmpxchg-optimization.ll

Issue 1312433004: Weight variables by their number of uses for register allocation. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 3 months ago
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1 ; This tests the optimization of atomic cmpxchg w/ following cmp + branches. 1 ; This tests the optimization of atomic cmpxchg w/ following cmp + branches.
2 2
3 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ 3 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
4 ; RUN: | FileCheck --check-prefix=O2 %s 4 ; RUN: | FileCheck --check-prefix=O2 %s
5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
6 ; RUN: | FileCheck --check-prefix=OM1 %s 6 ; RUN: | FileCheck --check-prefix=OM1 %s
7 7
8 declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32) 8 declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32)
9 9
10 10
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121 i32 %desired, i32 6, i32 6) 121 i32 %desired, i32 6, i32 6)
122 %success = icmp eq i32 %old, %expected 122 %success = icmp eq i32 %old, %expected
123 br i1 %success, label %done, label %loop 123 br i1 %success, label %done, label %loop
124 124
125 done: 125 done:
126 %r = zext i1 %success to i32 126 %r = zext i1 %success to i32
127 ret i32 %r 127 ret i32 %r
128 } 128 }
129 ; O2-LABEL: test_atomic_cmpxchg_no_opt2 129 ; O2-LABEL: test_atomic_cmpxchg_no_opt2
130 ; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}} 130 ; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
131 ; O2: mov {{.*}}
ascull 2015/08/26 19:24:36 Discussed with Jan. This used to match a register
132 ; O2: cmp 131 ; O2: cmp
133 ; O2: sete 132 ; O2: sete
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