Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(375)

Side by Side Diff: runtime/vm/instructions_mips.cc

Issue 131103025: Fixes ABI bug in MIPS. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years, 10 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch | Annotate | Revision Log
« no previous file with comments | « runtime/vm/assembler_mips.cc ('k') | runtime/vm/stub_code_mips.cc » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_MIPS. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_MIPS.
6 #if defined(TARGET_ARCH_MIPS) 6 #if defined(TARGET_ARCH_MIPS)
7 7
8 #include "vm/constants_mips.h" 8 #include "vm/constants_mips.h"
9 #include "vm/cpu.h" 9 #include "vm/cpu.h"
10 #include "vm/instructions.h" 10 #include "vm/instructions.h"
11 #include "vm/object.h" 11 #include "vm/object.h"
12 12
13 namespace dart { 13 namespace dart {
14 14
15 CallPattern::CallPattern(uword pc, const Code& code) 15 CallPattern::CallPattern(uword pc, const Code& code)
16 : object_pool_(Array::Handle(code.ObjectPool())), 16 : object_pool_(Array::Handle(code.ObjectPool())),
17 end_(pc), 17 end_(pc),
18 args_desc_load_end_(0), 18 args_desc_load_end_(0),
19 ic_data_load_end_(0), 19 ic_data_load_end_(0),
20 target_address_pool_index_(-1), 20 target_address_pool_index_(-1),
21 args_desc_(Array::Handle()), 21 args_desc_(Array::Handle()),
22 ic_data_(ICData::Handle()) { 22 ic_data_(ICData::Handle()) {
23 ASSERT(code.ContainsInstructionAt(pc)); 23 ASSERT(code.ContainsInstructionAt(pc));
24 // Last instruction: jalr RA, TMP(=R1). 24 // Last instruction: jalr RA, T9(=R25).
25 ASSERT(*(reinterpret_cast<uword*>(end_) - 2) == 0x0020f809); 25 ASSERT(*(reinterpret_cast<uword*>(end_) - 2) == 0x0320f809);
26 Register reg; 26 Register reg;
27 // The end of the pattern is the instruction after the delay slot of the jalr. 27 // The end of the pattern is the instruction after the delay slot of the jalr.
28 ic_data_load_end_ = 28 ic_data_load_end_ =
29 InstructionPattern::DecodeLoadWordFromPool(end_ - (2 * Instr::kInstrSize), 29 InstructionPattern::DecodeLoadWordFromPool(end_ - (2 * Instr::kInstrSize),
30 &reg, 30 &reg,
31 &target_address_pool_index_); 31 &target_address_pool_index_);
32 ASSERT(reg == TMP); 32 ASSERT(reg == T9);
33 } 33 }
34 34
35 35
36 // Decodes a load sequence ending at 'end' (the last instruction of the load 36 // Decodes a load sequence ending at 'end' (the last instruction of the load
37 // sequence is the instruction before the one at end). Returns a pointer to 37 // sequence is the instruction before the one at end). Returns a pointer to
38 // the first instruction in the sequence. Returns the register being loaded 38 // the first instruction in the sequence. Returns the register being loaded
39 // and the loaded object in the output parameters 'reg' and 'obj' 39 // and the loaded object in the output parameters 'reg' and 'obj'
40 // respectively. 40 // respectively.
41 uword InstructionPattern::DecodeLoadObject(uword end, 41 uword InstructionPattern::DecodeLoadObject(uword end,
42 const Array& object_pool, 42 const Array& object_pool,
(...skipping 130 matching lines...) Expand 10 before | Expand all | Expand 10 after
173 173
174 174
175 void CallPattern::InsertAt(uword pc, uword target_address) { 175 void CallPattern::InsertAt(uword pc, uword target_address) {
176 Instr* lui = Instr::At(pc + (0 * Instr::kInstrSize)); 176 Instr* lui = Instr::At(pc + (0 * Instr::kInstrSize));
177 Instr* ori = Instr::At(pc + (1 * Instr::kInstrSize)); 177 Instr* ori = Instr::At(pc + (1 * Instr::kInstrSize));
178 Instr* jr = Instr::At(pc + (2 * Instr::kInstrSize)); 178 Instr* jr = Instr::At(pc + (2 * Instr::kInstrSize));
179 Instr* nop = Instr::At(pc + (3 * Instr::kInstrSize)); 179 Instr* nop = Instr::At(pc + (3 * Instr::kInstrSize));
180 uint16_t target_lo = target_address & 0xffff; 180 uint16_t target_lo = target_address & 0xffff;
181 uint16_t target_hi = target_address >> 16; 181 uint16_t target_hi = target_address >> 16;
182 182
183 lui->SetImmInstrBits(LUI, ZR, TMP, target_hi); 183 lui->SetImmInstrBits(LUI, ZR, T9, target_hi);
184 ori->SetImmInstrBits(ORI, TMP, TMP, target_lo); 184 ori->SetImmInstrBits(ORI, T9, T9, target_lo);
185 jr->SetSpecialInstrBits(JALR, TMP, ZR, RA); 185 jr->SetSpecialInstrBits(JALR, T9, ZR, RA);
186 nop->SetInstructionBits(Instr::kNopInstruction); 186 nop->SetInstructionBits(Instr::kNopInstruction);
187 187
188 ASSERT(kFixedLengthInBytes == 4 * Instr::kInstrSize); 188 ASSERT(kFixedLengthInBytes == 4 * Instr::kInstrSize);
189 CPU::FlushICache(pc, kFixedLengthInBytes); 189 CPU::FlushICache(pc, kFixedLengthInBytes);
190 } 190 }
191 191
192 192
193 JumpPattern::JumpPattern(uword pc, const Code& code) : pc_(pc) { } 193 JumpPattern::JumpPattern(uword pc, const Code& code) : pc_(pc) { }
194 194
195 195
(...skipping 27 matching lines...) Expand all
223 const uint16_t target_lo = target_address & 0xffff; 223 const uint16_t target_lo = target_address & 0xffff;
224 const uint16_t target_hi = target_address >> 16; 224 const uint16_t target_hi = target_address >> 16;
225 225
226 lui->SetInstructionBits((lui_bits & 0xffff0000) | target_hi); 226 lui->SetInstructionBits((lui_bits & 0xffff0000) | target_hi);
227 ori->SetInstructionBits((ori_bits & 0xffff0000) | target_lo); 227 ori->SetInstructionBits((ori_bits & 0xffff0000) | target_lo);
228 } 228 }
229 229
230 } // namespace dart 230 } // namespace dart
231 231
232 #endif // defined TARGET_ARCH_MIPS 232 #endif // defined TARGET_ARCH_MIPS
OLDNEW
« no previous file with comments | « runtime/vm/assembler_mips.cc ('k') | runtime/vm/stub_code_mips.cc » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698