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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <limits.h> | 5 #include <limits.h> |
6 #include <stdarg.h> | 6 #include <stdarg.h> |
7 #include <stdlib.h> | 7 #include <stdlib.h> |
8 #include <cmath> | 8 #include <cmath> |
9 | 9 |
10 #if V8_TARGET_ARCH_MIPS | 10 #if V8_TARGET_ARCH_MIPS |
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972 | 972 |
973 // The sp is initialized to point to the bottom (high address) of the | 973 // The sp is initialized to point to the bottom (high address) of the |
974 // allocated stack area. To be safe in potential stack underflows we leave | 974 // allocated stack area. To be safe in potential stack underflows we leave |
975 // some buffer below. | 975 // some buffer below. |
976 registers_[sp] = reinterpret_cast<int32_t>(stack_) + stack_size_ - 64; | 976 registers_[sp] = reinterpret_cast<int32_t>(stack_) + stack_size_ - 64; |
977 // The ra and pc are initialized to a known bad value that will cause an | 977 // The ra and pc are initialized to a known bad value that will cause an |
978 // access violation if the simulator ever tries to execute it. | 978 // access violation if the simulator ever tries to execute it. |
979 registers_[pc] = bad_ra; | 979 registers_[pc] = bad_ra; |
980 registers_[ra] = bad_ra; | 980 registers_[ra] = bad_ra; |
981 InitializeCoverage(); | 981 InitializeCoverage(); |
982 for (int i = 0; i < kNumExceptions; i++) { | |
983 exceptions[i] = 0; | |
984 } | |
985 | |
986 last_debugger_input_ = NULL; | 982 last_debugger_input_ = NULL; |
987 } | 983 } |
988 | 984 |
989 | 985 |
990 Simulator::~Simulator() { free(stack_); } | 986 Simulator::~Simulator() { free(stack_); } |
991 | 987 |
992 | 988 |
993 // When the generated code calls an external reference we need to catch that in | 989 // When the generated code calls an external reference we need to catch that in |
994 // the simulator. The external reference will be a function compiled for the | 990 // the simulator. The external reference will be a function compiled for the |
995 // host architecture. We need to call that function instead of trying to | 991 // host architecture. We need to call that function instead of trying to |
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1621 void Simulator::TraceRegWr(int32_t value) { | 1617 void Simulator::TraceRegWr(int32_t value) { |
1622 if (::v8::internal::FLAG_trace_sim) { | 1618 if (::v8::internal::FLAG_trace_sim) { |
1623 SNPrintF(trace_buf_, "%08x", value); | 1619 SNPrintF(trace_buf_, "%08x", value); |
1624 } | 1620 } |
1625 } | 1621 } |
1626 | 1622 |
1627 | 1623 |
1628 // TODO(plind): consider making icount_ printing a flag option. | 1624 // TODO(plind): consider making icount_ printing a flag option. |
1629 void Simulator::TraceMemRd(int32_t addr, int32_t value) { | 1625 void Simulator::TraceMemRd(int32_t addr, int32_t value) { |
1630 if (::v8::internal::FLAG_trace_sim) { | 1626 if (::v8::internal::FLAG_trace_sim) { |
1631 SNPrintF(trace_buf_, "%08x <-- [%08x] (%d)", value, addr, icount_); | 1627 SNPrintF(trace_buf_, "%08x <-- [%08x] (%" PRIu64 ")", value, addr, |
| 1628 icount_); |
1632 } | 1629 } |
1633 } | 1630 } |
1634 | 1631 |
1635 | 1632 |
1636 void Simulator::TraceMemWr(int32_t addr, int32_t value, TraceType t) { | 1633 void Simulator::TraceMemWr(int32_t addr, int32_t value, TraceType t) { |
1637 if (::v8::internal::FLAG_trace_sim) { | 1634 if (::v8::internal::FLAG_trace_sim) { |
1638 switch (t) { | 1635 switch (t) { |
1639 case BYTE: | 1636 case BYTE: |
1640 SNPrintF(trace_buf_, " %02x --> [%08x]", | 1637 SNPrintF(trace_buf_, " %02x --> [%08x]", |
1641 static_cast<int8_t>(value), addr); | 1638 static_cast<int8_t>(value), addr); |
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2094 | 2091 |
2095 // Stop helper functions. | 2092 // Stop helper functions. |
2096 bool Simulator::IsWatchpoint(uint32_t code) { | 2093 bool Simulator::IsWatchpoint(uint32_t code) { |
2097 return (code <= kMaxWatchpointCode); | 2094 return (code <= kMaxWatchpointCode); |
2098 } | 2095 } |
2099 | 2096 |
2100 | 2097 |
2101 void Simulator::PrintWatchpoint(uint32_t code) { | 2098 void Simulator::PrintWatchpoint(uint32_t code) { |
2102 MipsDebugger dbg(this); | 2099 MipsDebugger dbg(this); |
2103 ++break_count_; | 2100 ++break_count_; |
2104 PrintF("\n---- break %d marker: %3d (instr count: %8d) ----------" | 2101 PrintF("\n---- break %d marker: %3d (instr count: %" PRIu64 |
| 2102 ") ----------" |
2105 "----------------------------------", | 2103 "----------------------------------", |
2106 code, break_count_, icount_); | 2104 code, break_count_, icount_); |
2107 dbg.PrintAllRegs(); // Print registers and continue running. | 2105 dbg.PrintAllRegs(); // Print registers and continue running. |
2108 } | 2106 } |
2109 | 2107 |
2110 | 2108 |
2111 void Simulator::HandleStop(uint32_t code, Instruction* instr) { | 2109 void Simulator::HandleStop(uint32_t code, Instruction* instr) { |
2112 // Stop if it is enabled, otherwise go on jumping over the stop | 2110 // Stop if it is enabled, otherwise go on jumping over the stop |
2113 // and the message address. | 2111 // and the message address. |
2114 if (IsEnabledStop(code)) { | 2112 if (IsEnabledStop(code)) { |
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2178 PrintF("stop %i - 0x%x: \t%s, \tcounter = %i, \t%s\n", | 2176 PrintF("stop %i - 0x%x: \t%s, \tcounter = %i, \t%s\n", |
2179 code, code, state, count, watched_stops_[code].desc); | 2177 code, code, state, count, watched_stops_[code].desc); |
2180 } else { | 2178 } else { |
2181 PrintF("stop %i - 0x%x: \t%s, \tcounter = %i\n", | 2179 PrintF("stop %i - 0x%x: \t%s, \tcounter = %i\n", |
2182 code, code, state, count); | 2180 code, code, state, count); |
2183 } | 2181 } |
2184 } | 2182 } |
2185 } | 2183 } |
2186 | 2184 |
2187 | 2185 |
2188 void Simulator::SignalExceptions() { | 2186 void Simulator::SignalException(Exception e) { |
2189 for (int i = 1; i < kNumExceptions; i++) { | 2187 V8_Fatal(__FILE__, __LINE__, "Error: Exception %i raised.", |
2190 if (exceptions[i] != 0) { | 2188 static_cast<int>(e)); |
2191 V8_Fatal(__FILE__, __LINE__, "Error: Exception %i raised.", i); | |
2192 } | |
2193 } | |
2194 } | 2189 } |
2195 | 2190 |
2196 | 2191 |
2197 // Handle execution based on instruction types. | 2192 void Simulator::DecodeTypeRegisterDRsType() { |
2198 | |
2199 void Simulator::ConfigureTypeRegister(Instruction* instr, | |
2200 int32_t* alu_out, | |
2201 int64_t* i64hilo, | |
2202 uint64_t* u64hilo, | |
2203 int32_t* next_pc, | |
2204 int32_t* return_addr_reg, | |
2205 bool* do_interrupt) { | |
2206 // Every local variable declared here needs to be const. | |
2207 // This is to make sure that changed values are sent back to | |
2208 // DecodeTypeRegister correctly. | |
2209 | |
2210 // Instruction fields. | |
2211 const Opcode op = instr->OpcodeFieldRaw(); | |
2212 const int32_t rs_reg = instr->RsValue(); | |
2213 const int32_t rs = get_register(rs_reg); | |
2214 const uint32_t rs_u = static_cast<uint32_t>(rs); | |
2215 const int32_t rt_reg = instr->RtValue(); | |
2216 const int32_t rt = get_register(rt_reg); | |
2217 const uint32_t rt_u = static_cast<uint32_t>(rt); | |
2218 const int32_t rd_reg = instr->RdValue(); | |
2219 const uint32_t sa = instr->SaValue(); | |
2220 const uint8_t bp = instr->Bp2Value(); | |
2221 | |
2222 const int32_t fs_reg = instr->FsValue(); | |
2223 | |
2224 | |
2225 // ---------- Configuration. | |
2226 switch (op) { | |
2227 case COP1: // Coprocessor instructions. | |
2228 switch (instr->RsFieldRaw()) { | |
2229 case CFC1: | |
2230 // At the moment only FCSR is supported. | |
2231 DCHECK(fs_reg == kFCSRRegister); | |
2232 *alu_out = FCSR_; | |
2233 break; | |
2234 case MFC1: | |
2235 *alu_out = get_fpu_register_word(fs_reg); | |
2236 break; | |
2237 case MFHC1: | |
2238 *alu_out = get_fpu_register_hi_word(fs_reg); | |
2239 break; | |
2240 case CTC1: | |
2241 case MTC1: | |
2242 case MTHC1: | |
2243 case S: | |
2244 case D: | |
2245 case W: | |
2246 case L: | |
2247 case PS: | |
2248 // Do everything in the execution step. | |
2249 break; | |
2250 default: | |
2251 // BC1 BC1EQZ BC1NEZ handled in DecodeTypeImmed, should never come here. | |
2252 UNREACHABLE(); | |
2253 } | |
2254 break; | |
2255 case COP1X: | |
2256 break; | |
2257 case SPECIAL: | |
2258 switch (instr->FunctionFieldRaw()) { | |
2259 case JR: | |
2260 case JALR: | |
2261 *next_pc = get_register(instr->RsValue()); | |
2262 *return_addr_reg = instr->RdValue(); | |
2263 break; | |
2264 case SLL: | |
2265 *alu_out = rt << sa; | |
2266 break; | |
2267 case SRL: | |
2268 if (rs_reg == 0) { | |
2269 // Regular logical right shift of a word by a fixed number of | |
2270 // bits instruction. RS field is always equal to 0. | |
2271 *alu_out = rt_u >> sa; | |
2272 } else { | |
2273 // Logical right-rotate of a word by a fixed number of bits. This | |
2274 // is special case of SRL instruction, added in MIPS32 Release 2. | |
2275 // RS field is equal to 00001. | |
2276 *alu_out = base::bits::RotateRight32(rt_u, sa); | |
2277 } | |
2278 break; | |
2279 case SRA: | |
2280 *alu_out = rt >> sa; | |
2281 break; | |
2282 case SLLV: | |
2283 *alu_out = rt << rs; | |
2284 break; | |
2285 case SRLV: | |
2286 if (sa == 0) { | |
2287 // Regular logical right-shift of a word by a variable number of | |
2288 // bits instruction. SA field is always equal to 0. | |
2289 *alu_out = rt_u >> rs; | |
2290 } else { | |
2291 // Logical right-rotate of a word by a variable number of bits. | |
2292 // This is special case od SRLV instruction, added in MIPS32 | |
2293 // Release 2. SA field is equal to 00001. | |
2294 *alu_out = base::bits::RotateRight32(rt_u, rs_u); | |
2295 } | |
2296 break; | |
2297 case SRAV: | |
2298 *alu_out = rt >> rs; | |
2299 break; | |
2300 case MFHI: // MFHI == CLZ on R6. | |
2301 if (!IsMipsArchVariant(kMips32r6)) { | |
2302 DCHECK(instr->SaValue() == 0); | |
2303 *alu_out = get_register(HI); | |
2304 } else { | |
2305 // MIPS spec: If no bits were set in GPR rs, the result written to | |
2306 // GPR rd is 32. | |
2307 DCHECK(instr->SaValue() == 1); | |
2308 *alu_out = base::bits::CountLeadingZeros32(rs_u); | |
2309 } | |
2310 break; | |
2311 case MFLO: | |
2312 *alu_out = get_register(LO); | |
2313 break; | |
2314 case MULT: // MULT == MUL_MUH. | |
2315 if (!IsMipsArchVariant(kMips32r6)) { | |
2316 *i64hilo = static_cast<int64_t>(rs) * static_cast<int64_t>(rt); | |
2317 } else { | |
2318 switch (instr->SaValue()) { | |
2319 case MUL_OP: | |
2320 case MUH_OP: | |
2321 *i64hilo = static_cast<int64_t>(rs) * static_cast<int64_t>(rt); | |
2322 break; | |
2323 default: | |
2324 UNIMPLEMENTED_MIPS(); | |
2325 break; | |
2326 } | |
2327 } | |
2328 break; | |
2329 case MULTU: // MULTU == MUL_MUH_U. | |
2330 if (!IsMipsArchVariant(kMips32r6)) { | |
2331 *u64hilo = static_cast<uint64_t>(rs_u) * | |
2332 static_cast<uint64_t>(rt_u); | |
2333 } else { | |
2334 switch (instr->SaValue()) { | |
2335 case MUL_OP: | |
2336 case MUH_OP: | |
2337 *u64hilo = static_cast<uint64_t>(rs_u) * | |
2338 static_cast<uint64_t>(rt_u); | |
2339 break; | |
2340 default: | |
2341 UNIMPLEMENTED_MIPS(); | |
2342 break; | |
2343 } | |
2344 } | |
2345 break; | |
2346 case ADD: | |
2347 if (HaveSameSign(rs, rt)) { | |
2348 if (rs > 0) { | |
2349 exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue - rt); | |
2350 } else if (rs < 0) { | |
2351 exceptions[kIntegerUnderflow] = rs < (Registers::kMinValue - rt); | |
2352 } | |
2353 } | |
2354 *alu_out = rs + rt; | |
2355 break; | |
2356 case ADDU: | |
2357 *alu_out = rs + rt; | |
2358 break; | |
2359 case SUB: | |
2360 if (!HaveSameSign(rs, rt)) { | |
2361 if (rs > 0) { | |
2362 exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue + rt); | |
2363 } else if (rs < 0) { | |
2364 exceptions[kIntegerUnderflow] = rs < (Registers::kMinValue + rt); | |
2365 } | |
2366 } | |
2367 *alu_out = rs - rt; | |
2368 break; | |
2369 case SUBU: | |
2370 *alu_out = rs - rt; | |
2371 break; | |
2372 case AND: | |
2373 *alu_out = rs & rt; | |
2374 break; | |
2375 case OR: | |
2376 *alu_out = rs | rt; | |
2377 break; | |
2378 case XOR: | |
2379 *alu_out = rs ^ rt; | |
2380 break; | |
2381 case NOR: | |
2382 *alu_out = ~(rs | rt); | |
2383 break; | |
2384 case SLT: | |
2385 *alu_out = rs < rt ? 1 : 0; | |
2386 break; | |
2387 case SLTU: | |
2388 *alu_out = rs_u < rt_u ? 1 : 0; | |
2389 break; | |
2390 // Break and trap instructions. | |
2391 case BREAK: | |
2392 *do_interrupt = true; | |
2393 break; | |
2394 case TGE: | |
2395 *do_interrupt = rs >= rt; | |
2396 break; | |
2397 case TGEU: | |
2398 *do_interrupt = rs_u >= rt_u; | |
2399 break; | |
2400 case TLT: | |
2401 *do_interrupt = rs < rt; | |
2402 break; | |
2403 case TLTU: | |
2404 *do_interrupt = rs_u < rt_u; | |
2405 break; | |
2406 case TEQ: | |
2407 *do_interrupt = rs == rt; | |
2408 break; | |
2409 case TNE: | |
2410 *do_interrupt = rs != rt; | |
2411 break; | |
2412 case MOVN: | |
2413 case MOVZ: | |
2414 case MOVCI: | |
2415 // No action taken on decode. | |
2416 break; | |
2417 case DIV: | |
2418 case DIVU: | |
2419 // div and divu never raise exceptions. | |
2420 case SELEQZ_S: | |
2421 case SELNEZ_S: | |
2422 break; | |
2423 default: | |
2424 UNREACHABLE(); | |
2425 } | |
2426 break; | |
2427 case SPECIAL2: | |
2428 switch (instr->FunctionFieldRaw()) { | |
2429 case MUL: | |
2430 *alu_out = rs_u * rt_u; // Only the lower 32 bits are kept. | |
2431 break; | |
2432 case CLZ: | |
2433 // MIPS32 spec: If no bits were set in GPR rs, the result written to | |
2434 // GPR rd is 32. | |
2435 *alu_out = base::bits::CountLeadingZeros32(rs_u); | |
2436 break; | |
2437 default: | |
2438 UNREACHABLE(); | |
2439 } | |
2440 break; | |
2441 case SPECIAL3: | |
2442 switch (instr->FunctionFieldRaw()) { | |
2443 case INS: { // Mips32r2 instruction. | |
2444 // Interpret rd field as 5-bit msb of insert. | |
2445 uint16_t msb = rd_reg; | |
2446 // Interpret sa field as 5-bit lsb of insert. | |
2447 uint16_t lsb = sa; | |
2448 uint16_t size = msb - lsb + 1; | |
2449 uint32_t mask = (1 << size) - 1; | |
2450 *alu_out = (rt_u & ~(mask << lsb)) | ((rs_u & mask) << lsb); | |
2451 break; | |
2452 } | |
2453 case EXT: { // Mips32r2 instruction. | |
2454 // Interpret rd field as 5-bit msb of extract. | |
2455 uint16_t msb = rd_reg; | |
2456 // Interpret sa field as 5-bit lsb of extract. | |
2457 uint16_t lsb = sa; | |
2458 uint16_t size = msb + 1; | |
2459 uint32_t mask = (1 << size) - 1; | |
2460 *alu_out = (rs_u & (mask << lsb)) >> lsb; | |
2461 break; | |
2462 } | |
2463 case BSHFL: { | |
2464 int sa = instr->SaFieldRaw() >> kSaShift; | |
2465 switch (sa) { | |
2466 case BITSWAP: { | |
2467 uint32_t input = static_cast<uint32_t>(rt); | |
2468 uint32_t output = 0; | |
2469 uint8_t i_byte, o_byte; | |
2470 | |
2471 // Reverse the bit in byte for each individual byte | |
2472 for (int i = 0; i < 4; i++) { | |
2473 output = output >> 8; | |
2474 i_byte = input & 0xff; | |
2475 | |
2476 // Fast way to reverse bits in byte | |
2477 // Devised by Sean Anderson, July 13, 2001 | |
2478 o_byte = | |
2479 static_cast<uint8_t>(((i_byte * 0x0802LU & 0x22110LU) | | |
2480 (i_byte * 0x8020LU & 0x88440LU)) * | |
2481 0x10101LU >> | |
2482 16); | |
2483 | |
2484 output = output | (static_cast<uint32_t>(o_byte << 24)); | |
2485 input = input >> 8; | |
2486 } | |
2487 | |
2488 *alu_out = static_cast<int32_t>(output); | |
2489 break; | |
2490 } | |
2491 case SEB: | |
2492 case SEH: | |
2493 case WSBH: | |
2494 UNREACHABLE(); | |
2495 break; | |
2496 default: { | |
2497 sa >>= kBp2Bits; | |
2498 switch (sa) { | |
2499 case ALIGN: { | |
2500 if (bp == 0) { | |
2501 *alu_out = static_cast<int32_t>(rt); | |
2502 } else { | |
2503 uint32_t rt_hi = rt << (8 * bp); | |
2504 uint32_t rs_lo = rs >> (8 * (4 - bp)); | |
2505 *alu_out = static_cast<int32_t>(rt_hi | rs_lo); | |
2506 } | |
2507 break; | |
2508 } | |
2509 default: | |
2510 UNREACHABLE(); | |
2511 break; | |
2512 } | |
2513 } | |
2514 } | |
2515 break; | |
2516 } | |
2517 default: | |
2518 UNREACHABLE(); | |
2519 } | |
2520 break; | |
2521 default: | |
2522 UNREACHABLE(); | |
2523 } | |
2524 } | |
2525 | |
2526 | |
2527 void Simulator::DecodeTypeRegisterDRsType(Instruction* instr, | |
2528 const int32_t& fr_reg, | |
2529 const int32_t& fs_reg, | |
2530 const int32_t& ft_reg, | |
2531 const int32_t& fd_reg) { | |
2532 double ft, fs, fd; | 2193 double ft, fs, fd; |
2533 uint32_t cc, fcsr_cc; | 2194 uint32_t cc, fcsr_cc; |
2534 int64_t i64; | 2195 int64_t i64; |
2535 fs = get_fpu_register_double(fs_reg); | 2196 fs = get_fpu_register_double(fs_reg()); |
2536 ft = (instr->FunctionFieldRaw() != MOVF) ? get_fpu_register_double(ft_reg) | 2197 ft = (get_instr()->FunctionFieldRaw() != MOVF) |
2537 : 0.0; | 2198 ? get_fpu_register_double(ft_reg()) |
2538 fd = get_fpu_register_double(fd_reg); | 2199 : 0.0; |
| 2200 fd = get_fpu_register_double(fd_reg()); |
2539 int64_t ft_int = bit_cast<int64_t>(ft); | 2201 int64_t ft_int = bit_cast<int64_t>(ft); |
2540 int64_t fd_int = bit_cast<int64_t>(fd); | 2202 int64_t fd_int = bit_cast<int64_t>(fd); |
2541 cc = instr->FCccValue(); | 2203 cc = get_instr()->FCccValue(); |
2542 fcsr_cc = get_fcsr_condition_bit(cc); | 2204 fcsr_cc = get_fcsr_condition_bit(cc); |
2543 switch (instr->FunctionFieldRaw()) { | 2205 switch (get_instr()->FunctionFieldRaw()) { |
2544 case RINT: { | 2206 case RINT: { |
2545 DCHECK(IsMipsArchVariant(kMips32r6)); | 2207 DCHECK(IsMipsArchVariant(kMips32r6)); |
2546 double result, temp, temp_result; | 2208 double result, temp, temp_result; |
2547 double upper = std::ceil(fs); | 2209 double upper = std::ceil(fs); |
2548 double lower = std::floor(fs); | 2210 double lower = std::floor(fs); |
2549 switch (get_fcsr_rounding_mode()) { | 2211 switch (get_fcsr_rounding_mode()) { |
2550 case kRoundToNearest: | 2212 case kRoundToNearest: |
2551 if (upper - fs < fs - lower) { | 2213 if (upper - fs < fs - lower) { |
2552 result = upper; | 2214 result = upper; |
2553 } else if (upper - fs > fs - lower) { | 2215 } else if (upper - fs > fs - lower) { |
(...skipping 11 matching lines...) Expand all Loading... |
2565 case kRoundToZero: | 2227 case kRoundToZero: |
2566 result = (fs > 0 ? lower : upper); | 2228 result = (fs > 0 ? lower : upper); |
2567 break; | 2229 break; |
2568 case kRoundToPlusInf: | 2230 case kRoundToPlusInf: |
2569 result = upper; | 2231 result = upper; |
2570 break; | 2232 break; |
2571 case kRoundToMinusInf: | 2233 case kRoundToMinusInf: |
2572 result = lower; | 2234 result = lower; |
2573 break; | 2235 break; |
2574 } | 2236 } |
2575 set_fpu_register_double(fd_reg, result); | 2237 set_fpu_register_double(fd_reg(), result); |
2576 if (result != fs) { | 2238 if (result != fs) { |
2577 set_fcsr_bit(kFCSRInexactFlagBit, true); | 2239 set_fcsr_bit(kFCSRInexactFlagBit, true); |
2578 } | 2240 } |
2579 break; | 2241 break; |
2580 } | 2242 } |
2581 case SEL: | 2243 case SEL: |
2582 DCHECK(IsMipsArchVariant(kMips32r6)); | 2244 DCHECK(IsMipsArchVariant(kMips32r6)); |
2583 set_fpu_register_double(fd_reg, (fd_int & 0x1) == 0 ? fs : ft); | 2245 set_fpu_register_double(fd_reg(), (fd_int & 0x1) == 0 ? fs : ft); |
2584 break; | 2246 break; |
2585 case SELEQZ_C: | 2247 case SELEQZ_C: |
2586 DCHECK(IsMipsArchVariant(kMips32r6)); | 2248 DCHECK(IsMipsArchVariant(kMips32r6)); |
2587 set_fpu_register_double(fd_reg, (ft_int & 0x1) == 0 ? fs : 0.0); | 2249 set_fpu_register_double(fd_reg(), (ft_int & 0x1) == 0 ? fs : 0.0); |
2588 break; | 2250 break; |
2589 case SELNEZ_C: | 2251 case SELNEZ_C: |
2590 DCHECK(IsMipsArchVariant(kMips32r6)); | 2252 DCHECK(IsMipsArchVariant(kMips32r6)); |
2591 set_fpu_register_double(fd_reg, (ft_int & 0x1) != 0 ? fs : 0.0); | 2253 set_fpu_register_double(fd_reg(), (ft_int & 0x1) != 0 ? fs : 0.0); |
2592 break; | 2254 break; |
2593 case MOVZ_C: { | 2255 case MOVZ_C: { |
2594 DCHECK(IsMipsArchVariant(kMips32r2)); | 2256 DCHECK(IsMipsArchVariant(kMips32r2)); |
2595 int32_t rt_reg = instr->RtValue(); | 2257 if (rt() == 0) { |
2596 int32_t rt = get_register(rt_reg); | 2258 set_fpu_register_double(fd_reg(), fs); |
2597 if (rt == 0) { | |
2598 set_fpu_register_double(fd_reg, fs); | |
2599 } | 2259 } |
2600 break; | 2260 break; |
2601 } | 2261 } |
2602 case MOVN_C: { | 2262 case MOVN_C: { |
2603 DCHECK(IsMipsArchVariant(kMips32r2)); | 2263 DCHECK(IsMipsArchVariant(kMips32r2)); |
2604 int32_t rt_reg = instr->RtValue(); | 2264 int32_t rt_reg = get_instr()->RtValue(); |
2605 int32_t rt = get_register(rt_reg); | 2265 int32_t rt = get_register(rt_reg); |
2606 if (rt != 0) { | 2266 if (rt != 0) { |
2607 set_fpu_register_double(fd_reg, fs); | 2267 set_fpu_register_double(fd_reg(), fs); |
2608 } | 2268 } |
2609 break; | 2269 break; |
2610 } | 2270 } |
2611 case MOVF: { | 2271 case MOVF: { |
2612 // Same function field for MOVT.D and MOVF.D | 2272 // Same function field for MOVT.D and MOVF.D |
2613 uint32_t ft_cc = (ft_reg >> 2) & 0x7; | 2273 uint32_t ft_cc = (ft_reg() >> 2) & 0x7; |
2614 ft_cc = get_fcsr_condition_bit(ft_cc); | 2274 ft_cc = get_fcsr_condition_bit(ft_cc); |
2615 if (instr->Bit(16)) { // Read Tf bit. | 2275 if (get_instr()->Bit(16)) { // Read Tf bit. |
2616 // MOVT.D | 2276 // MOVT.D |
2617 if (test_fcsr_bit(ft_cc)) set_fpu_register_double(fd_reg, fs); | 2277 if (test_fcsr_bit(ft_cc)) set_fpu_register_double(fd_reg(), fs); |
2618 } else { | 2278 } else { |
2619 // MOVF.D | 2279 // MOVF.D |
2620 if (!test_fcsr_bit(ft_cc)) set_fpu_register_double(fd_reg, fs); | 2280 if (!test_fcsr_bit(ft_cc)) set_fpu_register_double(fd_reg(), fs); |
2621 } | 2281 } |
2622 break; | 2282 break; |
2623 } | 2283 } |
2624 case MIN: | 2284 case MIN: |
2625 DCHECK(IsMipsArchVariant(kMips32r6)); | 2285 DCHECK(IsMipsArchVariant(kMips32r6)); |
2626 fs = get_fpu_register_double(fs_reg); | 2286 fs = get_fpu_register_double(fs_reg()); |
2627 if (std::isnan(fs) && std::isnan(ft)) { | 2287 if (std::isnan(fs) && std::isnan(ft)) { |
2628 set_fpu_register_double(fd_reg, fs); | 2288 set_fpu_register_double(fd_reg(), fs); |
2629 } else if (std::isnan(fs) && !std::isnan(ft)) { | 2289 } else if (std::isnan(fs) && !std::isnan(ft)) { |
2630 set_fpu_register_double(fd_reg, ft); | 2290 set_fpu_register_double(fd_reg(), ft); |
2631 } else if (!std::isnan(fs) && std::isnan(ft)) { | 2291 } else if (!std::isnan(fs) && std::isnan(ft)) { |
2632 set_fpu_register_double(fd_reg, fs); | 2292 set_fpu_register_double(fd_reg(), fs); |
2633 } else { | 2293 } else { |
2634 set_fpu_register_double(fd_reg, (fs >= ft) ? ft : fs); | 2294 set_fpu_register_double(fd_reg(), (fs >= ft) ? ft : fs); |
2635 } | 2295 } |
2636 break; | 2296 break; |
2637 case MINA: | 2297 case MINA: |
2638 DCHECK(IsMipsArchVariant(kMips32r6)); | 2298 DCHECK(IsMipsArchVariant(kMips32r6)); |
2639 fs = get_fpu_register_double(fs_reg); | 2299 fs = get_fpu_register_double(fs_reg()); |
2640 if (std::isnan(fs) && std::isnan(ft)) { | 2300 if (std::isnan(fs) && std::isnan(ft)) { |
2641 set_fpu_register_double(fd_reg, fs); | 2301 set_fpu_register_double(fd_reg(), fs); |
2642 } else if (std::isnan(fs) && !std::isnan(ft)) { | 2302 } else if (std::isnan(fs) && !std::isnan(ft)) { |
2643 set_fpu_register_double(fd_reg, ft); | 2303 set_fpu_register_double(fd_reg(), ft); |
2644 } else if (!std::isnan(fs) && std::isnan(ft)) { | 2304 } else if (!std::isnan(fs) && std::isnan(ft)) { |
2645 set_fpu_register_double(fd_reg, fs); | 2305 set_fpu_register_double(fd_reg(), fs); |
2646 } else { | 2306 } else { |
2647 double result; | 2307 double result; |
2648 if (fabs(fs) > fabs(ft)) { | 2308 if (fabs(fs) > fabs(ft)) { |
2649 result = ft; | 2309 result = ft; |
2650 } else if (fabs(fs) < fabs(ft)) { | 2310 } else if (fabs(fs) < fabs(ft)) { |
2651 result = fs; | 2311 result = fs; |
2652 } else { | 2312 } else { |
2653 result = (fs > ft ? fs : ft); | 2313 result = (fs > ft ? fs : ft); |
2654 } | 2314 } |
2655 set_fpu_register_double(fd_reg, result); | 2315 set_fpu_register_double(fd_reg(), result); |
2656 } | 2316 } |
2657 break; | 2317 break; |
2658 case MAXA: | 2318 case MAXA: |
2659 DCHECK(IsMipsArchVariant(kMips32r6)); | 2319 DCHECK(IsMipsArchVariant(kMips32r6)); |
2660 fs = get_fpu_register_double(fs_reg); | 2320 fs = get_fpu_register_double(fs_reg()); |
2661 if (std::isnan(fs) && std::isnan(ft)) { | 2321 if (std::isnan(fs) && std::isnan(ft)) { |
2662 set_fpu_register_double(fd_reg, fs); | 2322 set_fpu_register_double(fd_reg(), fs); |
2663 } else if (std::isnan(fs) && !std::isnan(ft)) { | 2323 } else if (std::isnan(fs) && !std::isnan(ft)) { |
2664 set_fpu_register_double(fd_reg, ft); | 2324 set_fpu_register_double(fd_reg(), ft); |
2665 } else if (!std::isnan(fs) && std::isnan(ft)) { | 2325 } else if (!std::isnan(fs) && std::isnan(ft)) { |
2666 set_fpu_register_double(fd_reg, fs); | 2326 set_fpu_register_double(fd_reg(), fs); |
2667 } else { | 2327 } else { |
2668 double result; | 2328 double result; |
2669 if (fabs(fs) < fabs(ft)) { | 2329 if (fabs(fs) < fabs(ft)) { |
2670 result = ft; | 2330 result = ft; |
2671 } else if (fabs(fs) > fabs(ft)) { | 2331 } else if (fabs(fs) > fabs(ft)) { |
2672 result = fs; | 2332 result = fs; |
2673 } else { | 2333 } else { |
2674 result = (fs > ft ? fs : ft); | 2334 result = (fs > ft ? fs : ft); |
2675 } | 2335 } |
2676 set_fpu_register_double(fd_reg, result); | 2336 set_fpu_register_double(fd_reg(), result); |
2677 } | 2337 } |
2678 break; | 2338 break; |
2679 case MAX: | 2339 case MAX: |
2680 DCHECK(IsMipsArchVariant(kMips32r6)); | 2340 DCHECK(IsMipsArchVariant(kMips32r6)); |
2681 fs = get_fpu_register_double(fs_reg); | 2341 fs = get_fpu_register_double(fs_reg()); |
2682 if (std::isnan(fs) && std::isnan(ft)) { | 2342 if (std::isnan(fs) && std::isnan(ft)) { |
2683 set_fpu_register_double(fd_reg, fs); | 2343 set_fpu_register_double(fd_reg(), fs); |
2684 } else if (std::isnan(fs) && !std::isnan(ft)) { | 2344 } else if (std::isnan(fs) && !std::isnan(ft)) { |
2685 set_fpu_register_double(fd_reg, ft); | 2345 set_fpu_register_double(fd_reg(), ft); |
2686 } else if (!std::isnan(fs) && std::isnan(ft)) { | 2346 } else if (!std::isnan(fs) && std::isnan(ft)) { |
2687 set_fpu_register_double(fd_reg, fs); | 2347 set_fpu_register_double(fd_reg(), fs); |
2688 } else { | 2348 } else { |
2689 set_fpu_register_double(fd_reg, (fs <= ft) ? ft : fs); | 2349 set_fpu_register_double(fd_reg(), (fs <= ft) ? ft : fs); |
2690 } | 2350 } |
2691 break; | 2351 break; |
2692 break; | 2352 break; |
2693 case ADD_D: | 2353 case ADD_D: |
2694 set_fpu_register_double(fd_reg, fs + ft); | 2354 set_fpu_register_double(fd_reg(), fs + ft); |
2695 break; | 2355 break; |
2696 case SUB_D: | 2356 case SUB_D: |
2697 set_fpu_register_double(fd_reg, fs - ft); | 2357 set_fpu_register_double(fd_reg(), fs - ft); |
2698 break; | 2358 break; |
2699 case MUL_D: | 2359 case MUL_D: |
2700 set_fpu_register_double(fd_reg, fs * ft); | 2360 set_fpu_register_double(fd_reg(), fs * ft); |
2701 break; | 2361 break; |
2702 case DIV_D: | 2362 case DIV_D: |
2703 set_fpu_register_double(fd_reg, fs / ft); | 2363 set_fpu_register_double(fd_reg(), fs / ft); |
2704 break; | 2364 break; |
2705 case ABS_D: | 2365 case ABS_D: |
2706 set_fpu_register_double(fd_reg, fabs(fs)); | 2366 set_fpu_register_double(fd_reg(), fabs(fs)); |
2707 break; | 2367 break; |
2708 case MOV_D: | 2368 case MOV_D: |
2709 set_fpu_register_double(fd_reg, fs); | 2369 set_fpu_register_double(fd_reg(), fs); |
2710 break; | 2370 break; |
2711 case NEG_D: | 2371 case NEG_D: |
2712 set_fpu_register_double(fd_reg, -fs); | 2372 set_fpu_register_double(fd_reg(), -fs); |
2713 break; | 2373 break; |
2714 case SQRT_D: | 2374 case SQRT_D: |
2715 set_fpu_register_double(fd_reg, fast_sqrt(fs)); | 2375 set_fpu_register_double(fd_reg(), fast_sqrt(fs)); |
2716 break; | 2376 break; |
2717 case RSQRT_D: { | 2377 case RSQRT_D: { |
2718 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); | 2378 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); |
2719 double result = 1.0 / fast_sqrt(fs); | 2379 double result = 1.0 / fast_sqrt(fs); |
2720 set_fpu_register_double(fd_reg, result); | 2380 set_fpu_register_double(fd_reg(), result); |
2721 break; | 2381 break; |
2722 } | 2382 } |
2723 case RECIP_D: { | 2383 case RECIP_D: { |
2724 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); | 2384 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); |
2725 double result = 1.0 / fs; | 2385 double result = 1.0 / fs; |
2726 set_fpu_register_double(fd_reg, result); | 2386 set_fpu_register_double(fd_reg(), result); |
2727 break; | 2387 break; |
2728 } | 2388 } |
2729 case C_UN_D: | 2389 case C_UN_D: |
2730 set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft)); | 2390 set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft)); |
2731 break; | 2391 break; |
2732 case C_EQ_D: | 2392 case C_EQ_D: |
2733 set_fcsr_bit(fcsr_cc, (fs == ft)); | 2393 set_fcsr_bit(fcsr_cc, (fs == ft)); |
2734 break; | 2394 break; |
2735 case C_UEQ_D: | 2395 case C_UEQ_D: |
2736 set_fcsr_bit(fcsr_cc, (fs == ft) || (std::isnan(fs) || std::isnan(ft))); | 2396 set_fcsr_bit(fcsr_cc, (fs == ft) || (std::isnan(fs) || std::isnan(ft))); |
2737 break; | 2397 break; |
2738 case C_OLT_D: | 2398 case C_OLT_D: |
2739 set_fcsr_bit(fcsr_cc, (fs < ft)); | 2399 set_fcsr_bit(fcsr_cc, (fs < ft)); |
2740 break; | 2400 break; |
2741 case C_ULT_D: | 2401 case C_ULT_D: |
2742 set_fcsr_bit(fcsr_cc, (fs < ft) || (std::isnan(fs) || std::isnan(ft))); | 2402 set_fcsr_bit(fcsr_cc, (fs < ft) || (std::isnan(fs) || std::isnan(ft))); |
2743 break; | 2403 break; |
2744 case C_OLE_D: | 2404 case C_OLE_D: |
2745 set_fcsr_bit(fcsr_cc, (fs <= ft)); | 2405 set_fcsr_bit(fcsr_cc, (fs <= ft)); |
2746 break; | 2406 break; |
2747 case C_ULE_D: | 2407 case C_ULE_D: |
2748 set_fcsr_bit(fcsr_cc, (fs <= ft) || (std::isnan(fs) || std::isnan(ft))); | 2408 set_fcsr_bit(fcsr_cc, (fs <= ft) || (std::isnan(fs) || std::isnan(ft))); |
2749 break; | 2409 break; |
2750 case CVT_W_D: { // Convert double to word. | 2410 case CVT_W_D: { // Convert double to word. |
2751 double rounded; | 2411 double rounded; |
2752 int32_t result; | 2412 int32_t result; |
2753 round_according_to_fcsr(fs, rounded, result, fs); | 2413 round_according_to_fcsr(fs, rounded, result, fs); |
2754 set_fpu_register_word(fd_reg, result); | 2414 set_fpu_register_word(fd_reg(), result); |
2755 if (set_fcsr_round_error(fs, rounded)) { | 2415 if (set_fcsr_round_error(fs, rounded)) { |
2756 set_fpu_register_word(fd_reg, kFPUInvalidResult); | 2416 set_fpu_register_word(fd_reg(), kFPUInvalidResult); |
2757 } | 2417 } |
2758 } break; | 2418 } break; |
2759 case ROUND_W_D: // Round double to word (round half to even). | 2419 case ROUND_W_D: // Round double to word (round half to even). |
2760 { | 2420 { |
2761 double rounded = std::floor(fs + 0.5); | 2421 double rounded = std::floor(fs + 0.5); |
2762 int32_t result = static_cast<int32_t>(rounded); | 2422 int32_t result = static_cast<int32_t>(rounded); |
2763 if ((result & 1) != 0 && result - fs == 0.5) { | 2423 if ((result & 1) != 0 && result - fs == 0.5) { |
2764 // If the number is halfway between two integers, | 2424 // If the number is halfway between two integers, |
2765 // round to the even one. | 2425 // round to the even one. |
2766 result--; | 2426 result--; |
2767 } | 2427 } |
2768 set_fpu_register_word(fd_reg, result); | 2428 set_fpu_register_word(fd_reg(), result); |
2769 if (set_fcsr_round_error(fs, rounded)) { | 2429 if (set_fcsr_round_error(fs, rounded)) { |
2770 set_fpu_register_word(fd_reg, kFPUInvalidResult); | 2430 set_fpu_register_word(fd_reg(), kFPUInvalidResult); |
2771 } | 2431 } |
2772 } break; | 2432 } break; |
2773 case TRUNC_W_D: // Truncate double to word (round towards 0). | 2433 case TRUNC_W_D: // Truncate double to word (round towards 0). |
2774 { | 2434 { |
2775 double rounded = trunc(fs); | 2435 double rounded = trunc(fs); |
2776 int32_t result = static_cast<int32_t>(rounded); | 2436 int32_t result = static_cast<int32_t>(rounded); |
2777 set_fpu_register_word(fd_reg, result); | 2437 set_fpu_register_word(fd_reg(), result); |
2778 if (set_fcsr_round_error(fs, rounded)) { | 2438 if (set_fcsr_round_error(fs, rounded)) { |
2779 set_fpu_register_word(fd_reg, kFPUInvalidResult); | 2439 set_fpu_register_word(fd_reg(), kFPUInvalidResult); |
2780 } | 2440 } |
2781 } break; | 2441 } break; |
2782 case FLOOR_W_D: // Round double to word towards negative infinity. | 2442 case FLOOR_W_D: // Round double to word towards negative infinity. |
2783 { | 2443 { |
2784 double rounded = std::floor(fs); | 2444 double rounded = std::floor(fs); |
2785 int32_t result = static_cast<int32_t>(rounded); | 2445 int32_t result = static_cast<int32_t>(rounded); |
2786 set_fpu_register_word(fd_reg, result); | 2446 set_fpu_register_word(fd_reg(), result); |
2787 if (set_fcsr_round_error(fs, rounded)) { | 2447 if (set_fcsr_round_error(fs, rounded)) { |
2788 set_fpu_register_word(fd_reg, kFPUInvalidResult); | 2448 set_fpu_register_word(fd_reg(), kFPUInvalidResult); |
2789 } | 2449 } |
2790 } break; | 2450 } break; |
2791 case CEIL_W_D: // Round double to word towards positive infinity. | 2451 case CEIL_W_D: // Round double to word towards positive infinity. |
2792 { | 2452 { |
2793 double rounded = std::ceil(fs); | 2453 double rounded = std::ceil(fs); |
2794 int32_t result = static_cast<int32_t>(rounded); | 2454 int32_t result = static_cast<int32_t>(rounded); |
2795 set_fpu_register_word(fd_reg, result); | 2455 set_fpu_register_word(fd_reg(), result); |
2796 if (set_fcsr_round_error(fs, rounded)) { | 2456 if (set_fcsr_round_error(fs, rounded)) { |
2797 set_fpu_register_word(fd_reg, kFPUInvalidResult); | 2457 set_fpu_register_word(fd_reg(), kFPUInvalidResult); |
2798 } | 2458 } |
2799 } break; | 2459 } break; |
2800 case CVT_S_D: // Convert double to float (single). | 2460 case CVT_S_D: // Convert double to float (single). |
2801 set_fpu_register_float(fd_reg, static_cast<float>(fs)); | 2461 set_fpu_register_float(fd_reg(), static_cast<float>(fs)); |
2802 break; | 2462 break; |
2803 case CVT_L_D: { // Mips32r2: Truncate double to 64-bit long-word. | 2463 case CVT_L_D: { // Mips32r2: Truncate double to 64-bit long-word. |
2804 if (IsFp64Mode()) { | 2464 if (IsFp64Mode()) { |
2805 int64_t result; | 2465 int64_t result; |
2806 double rounded; | 2466 double rounded; |
2807 round64_according_to_fcsr(fs, rounded, result, fs); | 2467 round64_according_to_fcsr(fs, rounded, result, fs); |
2808 set_fpu_register(fd_reg, result); | 2468 set_fpu_register(fd_reg(), result); |
2809 if (set_fcsr_round64_error(fs, rounded)) { | 2469 if (set_fcsr_round64_error(fs, rounded)) { |
2810 set_fpu_register(fd_reg, kFPU64InvalidResult); | 2470 set_fpu_register(fd_reg(), kFPU64InvalidResult); |
2811 } | 2471 } |
2812 } else { | 2472 } else { |
2813 UNSUPPORTED(); | 2473 UNSUPPORTED(); |
2814 } | 2474 } |
2815 break; | 2475 break; |
2816 break; | 2476 break; |
2817 } | 2477 } |
2818 case TRUNC_L_D: { // Mips32r2 instruction. | 2478 case TRUNC_L_D: { // Mips32r2 instruction. |
2819 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); | 2479 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); |
2820 double rounded = trunc(fs); | 2480 double rounded = trunc(fs); |
2821 i64 = static_cast<int64_t>(rounded); | 2481 i64 = static_cast<int64_t>(rounded); |
2822 if (IsFp64Mode()) { | 2482 if (IsFp64Mode()) { |
2823 set_fpu_register(fd_reg, i64); | 2483 set_fpu_register(fd_reg(), i64); |
2824 if (set_fcsr_round64_error(fs, rounded)) { | 2484 if (set_fcsr_round64_error(fs, rounded)) { |
2825 set_fpu_register(fd_reg, kFPU64InvalidResult); | 2485 set_fpu_register(fd_reg(), kFPU64InvalidResult); |
2826 } | 2486 } |
2827 } else { | 2487 } else { |
2828 UNSUPPORTED(); | 2488 UNSUPPORTED(); |
2829 } | 2489 } |
2830 break; | 2490 break; |
2831 } | 2491 } |
2832 case ROUND_L_D: { // Mips32r2 instruction. | 2492 case ROUND_L_D: { // Mips32r2 instruction. |
2833 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); | 2493 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); |
2834 double rounded = std::floor(fs + 0.5); | 2494 double rounded = std::floor(fs + 0.5); |
2835 int64_t result = static_cast<int64_t>(rounded); | 2495 int64_t result = static_cast<int64_t>(rounded); |
2836 if ((result & 1) != 0 && result - fs == 0.5) { | 2496 if ((result & 1) != 0 && result - fs == 0.5) { |
2837 // If the number is halfway between two integers, | 2497 // If the number is halfway between two integers, |
2838 // round to the even one. | 2498 // round to the even one. |
2839 result--; | 2499 result--; |
2840 } | 2500 } |
2841 int64_t i64 = static_cast<int64_t>(result); | 2501 int64_t i64 = static_cast<int64_t>(result); |
2842 if (IsFp64Mode()) { | 2502 if (IsFp64Mode()) { |
2843 set_fpu_register(fd_reg, i64); | 2503 set_fpu_register(fd_reg(), i64); |
2844 if (set_fcsr_round64_error(fs, rounded)) { | 2504 if (set_fcsr_round64_error(fs, rounded)) { |
2845 set_fpu_register(fd_reg, kFPU64InvalidResult); | 2505 set_fpu_register(fd_reg(), kFPU64InvalidResult); |
2846 } | 2506 } |
2847 } else { | 2507 } else { |
2848 UNSUPPORTED(); | 2508 UNSUPPORTED(); |
2849 } | 2509 } |
2850 break; | 2510 break; |
2851 } | 2511 } |
2852 case FLOOR_L_D: { // Mips32r2 instruction. | 2512 case FLOOR_L_D: { // Mips32r2 instruction. |
2853 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); | 2513 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); |
2854 double rounded = std::floor(fs); | 2514 double rounded = std::floor(fs); |
2855 int64_t i64 = static_cast<int64_t>(rounded); | 2515 int64_t i64 = static_cast<int64_t>(rounded); |
2856 if (IsFp64Mode()) { | 2516 if (IsFp64Mode()) { |
2857 set_fpu_register(fd_reg, i64); | 2517 set_fpu_register(fd_reg(), i64); |
2858 if (set_fcsr_round64_error(fs, rounded)) { | 2518 if (set_fcsr_round64_error(fs, rounded)) { |
2859 set_fpu_register(fd_reg, kFPU64InvalidResult); | 2519 set_fpu_register(fd_reg(), kFPU64InvalidResult); |
2860 } | 2520 } |
2861 } else { | 2521 } else { |
2862 UNSUPPORTED(); | 2522 UNSUPPORTED(); |
2863 } | 2523 } |
2864 break; | 2524 break; |
2865 } | 2525 } |
2866 case CEIL_L_D: { // Mips32r2 instruction. | 2526 case CEIL_L_D: { // Mips32r2 instruction. |
2867 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); | 2527 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); |
2868 double rounded = std::ceil(fs); | 2528 double rounded = std::ceil(fs); |
2869 int64_t i64 = static_cast<int64_t>(rounded); | 2529 int64_t i64 = static_cast<int64_t>(rounded); |
2870 if (IsFp64Mode()) { | 2530 if (IsFp64Mode()) { |
2871 set_fpu_register(fd_reg, i64); | 2531 set_fpu_register(fd_reg(), i64); |
2872 if (set_fcsr_round64_error(fs, rounded)) { | 2532 if (set_fcsr_round64_error(fs, rounded)) { |
2873 set_fpu_register(fd_reg, kFPU64InvalidResult); | 2533 set_fpu_register(fd_reg(), kFPU64InvalidResult); |
2874 } | 2534 } |
2875 } else { | 2535 } else { |
2876 UNSUPPORTED(); | 2536 UNSUPPORTED(); |
2877 } | 2537 } |
2878 break; | 2538 break; |
2879 } | 2539 } |
2880 case CLASS_D: { // Mips32r6 instruction | 2540 case CLASS_D: { // Mips32r6 instruction |
2881 // Convert double input to uint64_t for easier bit manipulation | 2541 // Convert double input to uint64_t for easier bit manipulation |
2882 uint64_t classed = bit_cast<uint64_t>(fs); | 2542 uint64_t classed = bit_cast<uint64_t>(fs); |
2883 | 2543 |
(...skipping 47 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2931 } | 2591 } |
2932 | 2592 |
2933 // Calculating result according to description of CLASS.D instruction | 2593 // Calculating result according to description of CLASS.D instruction |
2934 result = (posZero << 9) | (posSubnorm << 8) | (posNorm << 7) | | 2594 result = (posZero << 9) | (posSubnorm << 8) | (posNorm << 7) | |
2935 (posInf << 6) | (negZero << 5) | (negSubnorm << 4) | | 2595 (posInf << 6) | (negZero << 5) | (negSubnorm << 4) | |
2936 (negNorm << 3) | (negInf << 2) | (quietNan << 1) | signalingNan; | 2596 (negNorm << 3) | (negInf << 2) | (quietNan << 1) | signalingNan; |
2937 | 2597 |
2938 DCHECK(result != 0); | 2598 DCHECK(result != 0); |
2939 | 2599 |
2940 dResult = bit_cast<double>(result); | 2600 dResult = bit_cast<double>(result); |
2941 set_fpu_register_double(fd_reg, dResult); | 2601 set_fpu_register_double(fd_reg(), dResult); |
2942 | 2602 |
2943 break; | 2603 break; |
2944 } | 2604 } |
2945 case C_F_D: { | 2605 case C_F_D: { |
2946 set_fcsr_bit(fcsr_cc, false); | 2606 set_fcsr_bit(fcsr_cc, false); |
2947 break; | 2607 break; |
2948 } | 2608 } |
2949 default: | 2609 default: |
2950 UNREACHABLE(); | 2610 UNREACHABLE(); |
2951 } | 2611 } |
2952 } | 2612 } |
2953 | 2613 |
2954 | 2614 |
2955 void Simulator::DecodeTypeRegisterWRsType(Instruction* instr, int32_t& alu_out, | 2615 void Simulator::DecodeTypeRegisterWRsType() { |
2956 const int32_t& fd_reg, | 2616 float fs = get_fpu_register_float(fs_reg()); |
2957 const int32_t& fs_reg, | 2617 float ft = get_fpu_register_float(ft_reg()); |
2958 const int32_t& ft_reg) { | 2618 int32_t alu_out = 0x12345678; |
2959 float fs = get_fpu_register_float(fs_reg); | 2619 switch (get_instr()->FunctionFieldRaw()) { |
2960 float ft = get_fpu_register_float(ft_reg); | |
2961 switch (instr->FunctionFieldRaw()) { | |
2962 case CVT_S_W: // Convert word to float (single). | 2620 case CVT_S_W: // Convert word to float (single). |
2963 alu_out = get_fpu_register_signed_word(fs_reg); | 2621 alu_out = get_fpu_register_signed_word(fs_reg()); |
2964 set_fpu_register_float(fd_reg, static_cast<float>(alu_out)); | 2622 set_fpu_register_float(fd_reg(), static_cast<float>(alu_out)); |
2965 break; | 2623 break; |
2966 case CVT_D_W: // Convert word to double. | 2624 case CVT_D_W: // Convert word to double. |
2967 alu_out = get_fpu_register_signed_word(fs_reg); | 2625 alu_out = get_fpu_register_signed_word(fs_reg()); |
2968 set_fpu_register_double(fd_reg, static_cast<double>(alu_out)); | 2626 set_fpu_register_double(fd_reg(), static_cast<double>(alu_out)); |
2969 break; | 2627 break; |
2970 case CMP_AF: | 2628 case CMP_AF: |
2971 set_fpu_register_word(fd_reg, 0); | 2629 set_fpu_register_word(fd_reg(), 0); |
2972 break; | 2630 break; |
2973 case CMP_UN: | 2631 case CMP_UN: |
2974 if (std::isnan(fs) || std::isnan(ft)) { | 2632 if (std::isnan(fs) || std::isnan(ft)) { |
2975 set_fpu_register_word(fd_reg, -1); | 2633 set_fpu_register_word(fd_reg(), -1); |
2976 } else { | 2634 } else { |
2977 set_fpu_register_word(fd_reg, 0); | 2635 set_fpu_register_word(fd_reg(), 0); |
2978 } | 2636 } |
2979 break; | 2637 break; |
2980 case CMP_EQ: | 2638 case CMP_EQ: |
2981 if (fs == ft) { | 2639 if (fs == ft) { |
2982 set_fpu_register_word(fd_reg, -1); | 2640 set_fpu_register_word(fd_reg(), -1); |
2983 } else { | 2641 } else { |
2984 set_fpu_register_word(fd_reg, 0); | 2642 set_fpu_register_word(fd_reg(), 0); |
2985 } | 2643 } |
2986 break; | 2644 break; |
2987 case CMP_UEQ: | 2645 case CMP_UEQ: |
2988 if ((fs == ft) || (std::isnan(fs) || std::isnan(ft))) { | 2646 if ((fs == ft) || (std::isnan(fs) || std::isnan(ft))) { |
2989 set_fpu_register_word(fd_reg, -1); | 2647 set_fpu_register_word(fd_reg(), -1); |
2990 } else { | 2648 } else { |
2991 set_fpu_register_word(fd_reg, 0); | 2649 set_fpu_register_word(fd_reg(), 0); |
2992 } | 2650 } |
2993 break; | 2651 break; |
2994 case CMP_LT: | 2652 case CMP_LT: |
2995 if (fs < ft) { | 2653 if (fs < ft) { |
2996 set_fpu_register_word(fd_reg, -1); | 2654 set_fpu_register_word(fd_reg(), -1); |
2997 } else { | 2655 } else { |
2998 set_fpu_register_word(fd_reg, 0); | 2656 set_fpu_register_word(fd_reg(), 0); |
2999 } | 2657 } |
3000 break; | 2658 break; |
3001 case CMP_ULT: | 2659 case CMP_ULT: |
3002 if ((fs < ft) || (std::isnan(fs) || std::isnan(ft))) { | 2660 if ((fs < ft) || (std::isnan(fs) || std::isnan(ft))) { |
3003 set_fpu_register_word(fd_reg, -1); | 2661 set_fpu_register_word(fd_reg(), -1); |
3004 } else { | 2662 } else { |
3005 set_fpu_register_word(fd_reg, 0); | 2663 set_fpu_register_word(fd_reg(), 0); |
3006 } | 2664 } |
3007 break; | 2665 break; |
3008 case CMP_LE: | 2666 case CMP_LE: |
3009 if (fs <= ft) { | 2667 if (fs <= ft) { |
3010 set_fpu_register_word(fd_reg, -1); | 2668 set_fpu_register_word(fd_reg(), -1); |
3011 } else { | 2669 } else { |
3012 set_fpu_register_word(fd_reg, 0); | 2670 set_fpu_register_word(fd_reg(), 0); |
3013 } | 2671 } |
3014 break; | 2672 break; |
3015 case CMP_ULE: | 2673 case CMP_ULE: |
3016 if ((fs <= ft) || (std::isnan(fs) || std::isnan(ft))) { | 2674 if ((fs <= ft) || (std::isnan(fs) || std::isnan(ft))) { |
3017 set_fpu_register_word(fd_reg, -1); | 2675 set_fpu_register_word(fd_reg(), -1); |
3018 } else { | 2676 } else { |
3019 set_fpu_register_word(fd_reg, 0); | 2677 set_fpu_register_word(fd_reg(), 0); |
3020 } | 2678 } |
3021 break; | 2679 break; |
3022 case CMP_OR: | 2680 case CMP_OR: |
3023 if (!std::isnan(fs) && !std::isnan(ft)) { | 2681 if (!std::isnan(fs) && !std::isnan(ft)) { |
3024 set_fpu_register_word(fd_reg, -1); | 2682 set_fpu_register_word(fd_reg(), -1); |
3025 } else { | 2683 } else { |
3026 set_fpu_register_word(fd_reg, 0); | 2684 set_fpu_register_word(fd_reg(), 0); |
3027 } | 2685 } |
3028 break; | 2686 break; |
3029 case CMP_UNE: | 2687 case CMP_UNE: |
3030 if ((fs != ft) || (std::isnan(fs) || std::isnan(ft))) { | 2688 if ((fs != ft) || (std::isnan(fs) || std::isnan(ft))) { |
3031 set_fpu_register_word(fd_reg, -1); | 2689 set_fpu_register_word(fd_reg(), -1); |
3032 } else { | 2690 } else { |
3033 set_fpu_register_word(fd_reg, 0); | 2691 set_fpu_register_word(fd_reg(), 0); |
3034 } | 2692 } |
3035 break; | 2693 break; |
3036 case CMP_NE: | 2694 case CMP_NE: |
3037 if (fs != ft) { | 2695 if (fs != ft) { |
3038 set_fpu_register_word(fd_reg, -1); | 2696 set_fpu_register_word(fd_reg(), -1); |
3039 } else { | 2697 } else { |
3040 set_fpu_register_word(fd_reg, 0); | 2698 set_fpu_register_word(fd_reg(), 0); |
3041 } | 2699 } |
3042 break; | 2700 break; |
3043 default: | 2701 default: |
3044 UNREACHABLE(); | 2702 UNREACHABLE(); |
3045 } | 2703 } |
3046 } | 2704 } |
3047 | 2705 |
3048 | 2706 |
3049 void Simulator::DecodeTypeRegisterSRsType(Instruction* instr, | 2707 void Simulator::DecodeTypeRegisterSRsType() { |
3050 const int32_t& ft_reg, | |
3051 const int32_t& fs_reg, | |
3052 const int32_t& fd_reg) { | |
3053 float fs, ft, fd; | 2708 float fs, ft, fd; |
3054 fs = get_fpu_register_float(fs_reg); | 2709 fs = get_fpu_register_float(fs_reg()); |
3055 ft = get_fpu_register_float(ft_reg); | 2710 ft = get_fpu_register_float(ft_reg()); |
3056 fd = get_fpu_register_float(fd_reg); | 2711 fd = get_fpu_register_float(fd_reg()); |
3057 int32_t ft_int = bit_cast<int32_t>(ft); | 2712 int32_t ft_int = bit_cast<int32_t>(ft); |
3058 int32_t fd_int = bit_cast<int32_t>(fd); | 2713 int32_t fd_int = bit_cast<int32_t>(fd); |
3059 uint32_t cc, fcsr_cc; | 2714 uint32_t cc, fcsr_cc; |
3060 cc = instr->FCccValue(); | 2715 cc = get_instr()->FCccValue(); |
3061 fcsr_cc = get_fcsr_condition_bit(cc); | 2716 fcsr_cc = get_fcsr_condition_bit(cc); |
3062 switch (instr->FunctionFieldRaw()) { | 2717 switch (get_instr()->FunctionFieldRaw()) { |
3063 case RINT: { | 2718 case RINT: { |
3064 DCHECK(IsMipsArchVariant(kMips32r6)); | 2719 DCHECK(IsMipsArchVariant(kMips32r6)); |
3065 float result, temp_result; | 2720 float result, temp_result; |
3066 double temp; | 2721 double temp; |
3067 float upper = std::ceil(fs); | 2722 float upper = std::ceil(fs); |
3068 float lower = std::floor(fs); | 2723 float lower = std::floor(fs); |
3069 switch (get_fcsr_rounding_mode()) { | 2724 switch (get_fcsr_rounding_mode()) { |
3070 case kRoundToNearest: | 2725 case kRoundToNearest: |
3071 if (upper - fs < fs - lower) { | 2726 if (upper - fs < fs - lower) { |
3072 result = upper; | 2727 result = upper; |
(...skipping 12 matching lines...) Expand all Loading... |
3085 case kRoundToZero: | 2740 case kRoundToZero: |
3086 result = (fs > 0 ? lower : upper); | 2741 result = (fs > 0 ? lower : upper); |
3087 break; | 2742 break; |
3088 case kRoundToPlusInf: | 2743 case kRoundToPlusInf: |
3089 result = upper; | 2744 result = upper; |
3090 break; | 2745 break; |
3091 case kRoundToMinusInf: | 2746 case kRoundToMinusInf: |
3092 result = lower; | 2747 result = lower; |
3093 break; | 2748 break; |
3094 } | 2749 } |
3095 set_fpu_register_float(fd_reg, result); | 2750 set_fpu_register_float(fd_reg(), result); |
3096 if (result != fs) { | 2751 if (result != fs) { |
3097 set_fcsr_bit(kFCSRInexactFlagBit, true); | 2752 set_fcsr_bit(kFCSRInexactFlagBit, true); |
3098 } | 2753 } |
3099 break; | 2754 break; |
3100 } | 2755 } |
3101 case ADD_S: | 2756 case ADD_S: |
3102 set_fpu_register_float(fd_reg, fs + ft); | 2757 set_fpu_register_float(fd_reg(), fs + ft); |
3103 break; | 2758 break; |
3104 case SUB_S: | 2759 case SUB_S: |
3105 set_fpu_register_float(fd_reg, fs - ft); | 2760 set_fpu_register_float(fd_reg(), fs - ft); |
3106 break; | 2761 break; |
3107 case MUL_S: | 2762 case MUL_S: |
3108 set_fpu_register_float(fd_reg, fs * ft); | 2763 set_fpu_register_float(fd_reg(), fs * ft); |
3109 break; | 2764 break; |
3110 case DIV_S: | 2765 case DIV_S: |
3111 set_fpu_register_float(fd_reg, fs / ft); | 2766 set_fpu_register_float(fd_reg(), fs / ft); |
3112 break; | 2767 break; |
3113 case ABS_S: | 2768 case ABS_S: |
3114 set_fpu_register_float(fd_reg, fabs(fs)); | 2769 set_fpu_register_float(fd_reg(), fabs(fs)); |
3115 break; | 2770 break; |
3116 case MOV_S: | 2771 case MOV_S: |
3117 set_fpu_register_float(fd_reg, fs); | 2772 set_fpu_register_float(fd_reg(), fs); |
3118 break; | 2773 break; |
3119 case NEG_S: | 2774 case NEG_S: |
3120 set_fpu_register_float(fd_reg, -fs); | 2775 set_fpu_register_float(fd_reg(), -fs); |
3121 break; | 2776 break; |
3122 case SQRT_S: | 2777 case SQRT_S: |
3123 set_fpu_register_float(fd_reg, fast_sqrt(fs)); | 2778 set_fpu_register_float(fd_reg(), fast_sqrt(fs)); |
3124 break; | 2779 break; |
3125 case RSQRT_S: { | 2780 case RSQRT_S: { |
3126 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); | 2781 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); |
3127 float result = 1.0 / fast_sqrt(fs); | 2782 float result = 1.0 / fast_sqrt(fs); |
3128 set_fpu_register_float(fd_reg, result); | 2783 set_fpu_register_float(fd_reg(), result); |
3129 break; | 2784 break; |
3130 } | 2785 } |
3131 case RECIP_S: { | 2786 case RECIP_S: { |
3132 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); | 2787 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); |
3133 float result = 1.0 / fs; | 2788 float result = 1.0 / fs; |
3134 set_fpu_register_float(fd_reg, result); | 2789 set_fpu_register_float(fd_reg(), result); |
3135 break; | 2790 break; |
3136 } | 2791 } |
3137 case C_F_D: | 2792 case C_F_D: |
3138 set_fcsr_bit(fcsr_cc, false); | 2793 set_fcsr_bit(fcsr_cc, false); |
3139 break; | 2794 break; |
3140 case C_UN_D: | 2795 case C_UN_D: |
3141 set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft)); | 2796 set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft)); |
3142 break; | 2797 break; |
3143 case C_EQ_D: | 2798 case C_EQ_D: |
3144 set_fcsr_bit(fcsr_cc, (fs == ft)); | 2799 set_fcsr_bit(fcsr_cc, (fs == ft)); |
3145 break; | 2800 break; |
3146 case C_UEQ_D: | 2801 case C_UEQ_D: |
3147 set_fcsr_bit(fcsr_cc, (fs == ft) || (std::isnan(fs) || std::isnan(ft))); | 2802 set_fcsr_bit(fcsr_cc, (fs == ft) || (std::isnan(fs) || std::isnan(ft))); |
3148 break; | 2803 break; |
3149 case C_OLT_D: | 2804 case C_OLT_D: |
3150 set_fcsr_bit(fcsr_cc, (fs < ft)); | 2805 set_fcsr_bit(fcsr_cc, (fs < ft)); |
3151 break; | 2806 break; |
3152 case C_ULT_D: | 2807 case C_ULT_D: |
3153 set_fcsr_bit(fcsr_cc, (fs < ft) || (std::isnan(fs) || std::isnan(ft))); | 2808 set_fcsr_bit(fcsr_cc, (fs < ft) || (std::isnan(fs) || std::isnan(ft))); |
3154 break; | 2809 break; |
3155 case C_OLE_D: | 2810 case C_OLE_D: |
3156 set_fcsr_bit(fcsr_cc, (fs <= ft)); | 2811 set_fcsr_bit(fcsr_cc, (fs <= ft)); |
3157 break; | 2812 break; |
3158 case C_ULE_D: | 2813 case C_ULE_D: |
3159 set_fcsr_bit(fcsr_cc, (fs <= ft) || (std::isnan(fs) || std::isnan(ft))); | 2814 set_fcsr_bit(fcsr_cc, (fs <= ft) || (std::isnan(fs) || std::isnan(ft))); |
3160 break; | 2815 break; |
3161 case CVT_D_S: | 2816 case CVT_D_S: |
3162 set_fpu_register_double(fd_reg, static_cast<double>(fs)); | 2817 set_fpu_register_double(fd_reg(), static_cast<double>(fs)); |
3163 break; | 2818 break; |
3164 case SEL: | 2819 case SEL: |
3165 DCHECK(IsMipsArchVariant(kMips32r6)); | 2820 DCHECK(IsMipsArchVariant(kMips32r6)); |
3166 set_fpu_register_float(fd_reg, (fd_int & 0x1) == 0 ? fs : ft); | 2821 set_fpu_register_float(fd_reg(), (fd_int & 0x1) == 0 ? fs : ft); |
3167 break; | 2822 break; |
3168 case CLASS_S: { // Mips32r6 instruction | 2823 case CLASS_S: { // Mips32r6 instruction |
3169 // Convert float input to uint32_t for easier bit manipulation | 2824 // Convert float input to uint32_t for easier bit manipulation |
3170 float fs = get_fpu_register_float(fs_reg); | 2825 float fs = get_fpu_register_float(fs_reg()); |
3171 uint32_t classed = bit_cast<uint32_t>(fs); | 2826 uint32_t classed = bit_cast<uint32_t>(fs); |
3172 | 2827 |
3173 // Extracting sign, exponent and mantissa from the input float | 2828 // Extracting sign, exponent and mantissa from the input float |
3174 uint32_t sign = (classed >> 31) & 1; | 2829 uint32_t sign = (classed >> 31) & 1; |
3175 uint32_t exponent = (classed >> 23) & 0x000000ff; | 2830 uint32_t exponent = (classed >> 23) & 0x000000ff; |
3176 uint32_t mantissa = classed & 0x007fffff; | 2831 uint32_t mantissa = classed & 0x007fffff; |
3177 uint32_t result; | 2832 uint32_t result; |
3178 float fResult; | 2833 float fResult; |
3179 | 2834 |
3180 // Setting flags if input float is negative infinity, | 2835 // Setting flags if input float is negative infinity, |
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
3220 } | 2875 } |
3221 | 2876 |
3222 // Calculating result according to description of CLASS.S instruction | 2877 // Calculating result according to description of CLASS.S instruction |
3223 result = (posZero << 9) | (posSubnorm << 8) | (posNorm << 7) | | 2878 result = (posZero << 9) | (posSubnorm << 8) | (posNorm << 7) | |
3224 (posInf << 6) | (negZero << 5) | (negSubnorm << 4) | | 2879 (posInf << 6) | (negZero << 5) | (negSubnorm << 4) | |
3225 (negNorm << 3) | (negInf << 2) | (quietNan << 1) | signalingNan; | 2880 (negNorm << 3) | (negInf << 2) | (quietNan << 1) | signalingNan; |
3226 | 2881 |
3227 DCHECK(result != 0); | 2882 DCHECK(result != 0); |
3228 | 2883 |
3229 fResult = bit_cast<float>(result); | 2884 fResult = bit_cast<float>(result); |
3230 set_fpu_register_float(fd_reg, fResult); | 2885 set_fpu_register_float(fd_reg(), fResult); |
3231 | 2886 |
3232 break; | 2887 break; |
3233 } | 2888 } |
3234 case SELEQZ_C: | 2889 case SELEQZ_C: |
3235 DCHECK(IsMipsArchVariant(kMips32r6)); | 2890 DCHECK(IsMipsArchVariant(kMips32r6)); |
3236 set_fpu_register_float( | 2891 set_fpu_register_float(fd_reg(), (ft_int & 0x1) == 0 |
3237 fd_reg, (ft_int & 0x1) == 0 ? get_fpu_register_float(fs_reg) : 0.0); | 2892 ? get_fpu_register_float(fs_reg()) |
| 2893 : 0.0); |
3238 break; | 2894 break; |
3239 case SELNEZ_C: | 2895 case SELNEZ_C: |
3240 DCHECK(IsMipsArchVariant(kMips32r6)); | 2896 DCHECK(IsMipsArchVariant(kMips32r6)); |
3241 set_fpu_register_float( | 2897 set_fpu_register_float(fd_reg(), (ft_int & 0x1) != 0 |
3242 fd_reg, (ft_int & 0x1) != 0 ? get_fpu_register_float(fs_reg) : 0.0); | 2898 ? get_fpu_register_float(fs_reg()) |
| 2899 : 0.0); |
3243 break; | 2900 break; |
3244 case MOVZ_C: { | 2901 case MOVZ_C: { |
3245 DCHECK(IsMipsArchVariant(kMips32r2)); | 2902 DCHECK(IsMipsArchVariant(kMips32r2)); |
3246 int32_t rt_reg = instr->RtValue(); | 2903 if (rt() == 0) { |
3247 int32_t rt = get_register(rt_reg); | 2904 set_fpu_register_float(fd_reg(), fs); |
3248 if (rt == 0) { | |
3249 set_fpu_register_float(fd_reg, fs); | |
3250 } | 2905 } |
3251 break; | 2906 break; |
3252 } | 2907 } |
3253 case MOVN_C: { | 2908 case MOVN_C: { |
3254 DCHECK(IsMipsArchVariant(kMips32r2)); | 2909 DCHECK(IsMipsArchVariant(kMips32r2)); |
3255 int32_t rt_reg = instr->RtValue(); | 2910 if (rt() != 0) { |
3256 int32_t rt = get_register(rt_reg); | 2911 set_fpu_register_float(fd_reg(), fs); |
3257 if (rt != 0) { | |
3258 set_fpu_register_float(fd_reg, fs); | |
3259 } | 2912 } |
3260 break; | 2913 break; |
3261 } | 2914 } |
3262 case MOVF: { | 2915 case MOVF: { |
3263 // Same function field for MOVT.D and MOVF.D | 2916 // Same function field for MOVT.D and MOVF.D |
3264 uint32_t ft_cc = (ft_reg >> 2) & 0x7; | 2917 uint32_t ft_cc = (ft_reg() >> 2) & 0x7; |
3265 ft_cc = get_fcsr_condition_bit(ft_cc); | 2918 ft_cc = get_fcsr_condition_bit(ft_cc); |
3266 | 2919 |
3267 if (instr->Bit(16)) { // Read Tf bit. | 2920 if (get_instr()->Bit(16)) { // Read Tf bit. |
3268 // MOVT.D | 2921 // MOVT.D |
3269 if (test_fcsr_bit(ft_cc)) set_fpu_register_float(fd_reg, fs); | 2922 if (test_fcsr_bit(ft_cc)) set_fpu_register_float(fd_reg(), fs); |
3270 } else { | 2923 } else { |
3271 // MOVF.D | 2924 // MOVF.D |
3272 if (!test_fcsr_bit(ft_cc)) set_fpu_register_float(fd_reg, fs); | 2925 if (!test_fcsr_bit(ft_cc)) set_fpu_register_float(fd_reg(), fs); |
3273 } | 2926 } |
3274 break; | 2927 break; |
3275 } | 2928 } |
3276 case TRUNC_W_S: { // Truncate single to word (round towards 0). | 2929 case TRUNC_W_S: { // Truncate single to word (round towards 0). |
3277 float rounded = trunc(fs); | 2930 float rounded = trunc(fs); |
3278 int32_t result = static_cast<int32_t>(rounded); | 2931 int32_t result = static_cast<int32_t>(rounded); |
3279 set_fpu_register_word(fd_reg, result); | 2932 set_fpu_register_word(fd_reg(), result); |
3280 if (set_fcsr_round_error(fs, rounded)) { | 2933 if (set_fcsr_round_error(fs, rounded)) { |
3281 set_fpu_register_word(fd_reg, kFPUInvalidResult); | 2934 set_fpu_register_word(fd_reg(), kFPUInvalidResult); |
3282 } | 2935 } |
3283 } break; | 2936 } break; |
3284 case TRUNC_L_S: { // Mips32r2 instruction. | 2937 case TRUNC_L_S: { // Mips32r2 instruction. |
3285 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); | 2938 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); |
3286 float rounded = trunc(fs); | 2939 float rounded = trunc(fs); |
3287 int64_t i64 = static_cast<int64_t>(rounded); | 2940 int64_t i64 = static_cast<int64_t>(rounded); |
3288 if (IsFp64Mode()) { | 2941 if (IsFp64Mode()) { |
3289 set_fpu_register(fd_reg, i64); | 2942 set_fpu_register(fd_reg(), i64); |
3290 if (set_fcsr_round64_error(fs, rounded)) { | 2943 if (set_fcsr_round64_error(fs, rounded)) { |
3291 set_fpu_register(fd_reg, kFPU64InvalidResult); | 2944 set_fpu_register(fd_reg(), kFPU64InvalidResult); |
3292 } | 2945 } |
3293 } else { | 2946 } else { |
3294 UNSUPPORTED(); | 2947 UNSUPPORTED(); |
3295 } | 2948 } |
3296 break; | 2949 break; |
3297 } | 2950 } |
3298 case FLOOR_W_S: // Round double to word towards negative infinity. | 2951 case FLOOR_W_S: // Round double to word towards negative infinity. |
3299 { | 2952 { |
3300 float rounded = std::floor(fs); | 2953 float rounded = std::floor(fs); |
3301 int32_t result = static_cast<int32_t>(rounded); | 2954 int32_t result = static_cast<int32_t>(rounded); |
3302 set_fpu_register_word(fd_reg, result); | 2955 set_fpu_register_word(fd_reg(), result); |
3303 if (set_fcsr_round_error(fs, rounded)) { | 2956 if (set_fcsr_round_error(fs, rounded)) { |
3304 set_fpu_register_word(fd_reg, kFPUInvalidResult); | 2957 set_fpu_register_word(fd_reg(), kFPUInvalidResult); |
3305 } | 2958 } |
3306 } break; | 2959 } break; |
3307 case FLOOR_L_S: { // Mips32r2 instruction. | 2960 case FLOOR_L_S: { // Mips32r2 instruction. |
3308 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); | 2961 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); |
3309 float rounded = std::floor(fs); | 2962 float rounded = std::floor(fs); |
3310 int64_t i64 = static_cast<int64_t>(rounded); | 2963 int64_t i64 = static_cast<int64_t>(rounded); |
3311 if (IsFp64Mode()) { | 2964 if (IsFp64Mode()) { |
3312 set_fpu_register(fd_reg, i64); | 2965 set_fpu_register(fd_reg(), i64); |
3313 if (set_fcsr_round64_error(fs, rounded)) { | 2966 if (set_fcsr_round64_error(fs, rounded)) { |
3314 set_fpu_register(fd_reg, kFPU64InvalidResult); | 2967 set_fpu_register(fd_reg(), kFPU64InvalidResult); |
3315 } | 2968 } |
3316 } else { | 2969 } else { |
3317 UNSUPPORTED(); | 2970 UNSUPPORTED(); |
3318 } | 2971 } |
3319 break; | 2972 break; |
3320 } | 2973 } |
3321 case ROUND_W_S: { | 2974 case ROUND_W_S: { |
3322 float rounded = std::floor(fs + 0.5); | 2975 float rounded = std::floor(fs + 0.5); |
3323 int32_t result = static_cast<int32_t>(rounded); | 2976 int32_t result = static_cast<int32_t>(rounded); |
3324 if ((result & 1) != 0 && result - fs == 0.5) { | 2977 if ((result & 1) != 0 && result - fs == 0.5) { |
3325 // If the number is halfway between two integers, | 2978 // If the number is halfway between two integers, |
3326 // round to the even one. | 2979 // round to the even one. |
3327 result--; | 2980 result--; |
3328 } | 2981 } |
3329 set_fpu_register_word(fd_reg, result); | 2982 set_fpu_register_word(fd_reg(), result); |
3330 if (set_fcsr_round_error(fs, rounded)) { | 2983 if (set_fcsr_round_error(fs, rounded)) { |
3331 set_fpu_register_word(fd_reg, kFPUInvalidResult); | 2984 set_fpu_register_word(fd_reg(), kFPUInvalidResult); |
3332 } | 2985 } |
3333 break; | 2986 break; |
3334 } | 2987 } |
3335 case ROUND_L_S: { // Mips32r2 instruction. | 2988 case ROUND_L_S: { // Mips32r2 instruction. |
3336 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); | 2989 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); |
3337 float rounded = std::floor(fs + 0.5); | 2990 float rounded = std::floor(fs + 0.5); |
3338 int64_t result = static_cast<int64_t>(rounded); | 2991 int64_t result = static_cast<int64_t>(rounded); |
3339 if ((result & 1) != 0 && result - fs == 0.5) { | 2992 if ((result & 1) != 0 && result - fs == 0.5) { |
3340 // If the number is halfway between two integers, | 2993 // If the number is halfway between two integers, |
3341 // round to the even one. | 2994 // round to the even one. |
3342 result--; | 2995 result--; |
3343 } | 2996 } |
3344 int64_t i64 = static_cast<int64_t>(result); | 2997 int64_t i64 = static_cast<int64_t>(result); |
3345 if (IsFp64Mode()) { | 2998 if (IsFp64Mode()) { |
3346 set_fpu_register(fd_reg, i64); | 2999 set_fpu_register(fd_reg(), i64); |
3347 if (set_fcsr_round64_error(fs, rounded)) { | 3000 if (set_fcsr_round64_error(fs, rounded)) { |
3348 set_fpu_register(fd_reg, kFPU64InvalidResult); | 3001 set_fpu_register(fd_reg(), kFPU64InvalidResult); |
3349 } | 3002 } |
3350 } else { | 3003 } else { |
3351 UNSUPPORTED(); | 3004 UNSUPPORTED(); |
3352 } | 3005 } |
3353 break; | 3006 break; |
3354 } | 3007 } |
3355 case CEIL_W_S: // Round double to word towards positive infinity. | 3008 case CEIL_W_S: // Round double to word towards positive infinity. |
3356 { | 3009 { |
3357 float rounded = std::ceil(fs); | 3010 float rounded = std::ceil(fs); |
3358 int32_t result = static_cast<int32_t>(rounded); | 3011 int32_t result = static_cast<int32_t>(rounded); |
3359 set_fpu_register_word(fd_reg, result); | 3012 set_fpu_register_word(fd_reg(), result); |
3360 if (set_fcsr_round_error(fs, rounded)) { | 3013 if (set_fcsr_round_error(fs, rounded)) { |
3361 set_fpu_register_word(fd_reg, kFPUInvalidResult); | 3014 set_fpu_register_word(fd_reg(), kFPUInvalidResult); |
3362 } | 3015 } |
3363 } break; | 3016 } break; |
3364 case CEIL_L_S: { // Mips32r2 instruction. | 3017 case CEIL_L_S: { // Mips32r2 instruction. |
3365 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); | 3018 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); |
3366 float rounded = std::ceil(fs); | 3019 float rounded = std::ceil(fs); |
3367 int64_t i64 = static_cast<int64_t>(rounded); | 3020 int64_t i64 = static_cast<int64_t>(rounded); |
3368 if (IsFp64Mode()) { | 3021 if (IsFp64Mode()) { |
3369 set_fpu_register(fd_reg, i64); | 3022 set_fpu_register(fd_reg(), i64); |
3370 if (set_fcsr_round64_error(fs, rounded)) { | 3023 if (set_fcsr_round64_error(fs, rounded)) { |
3371 set_fpu_register(fd_reg, kFPU64InvalidResult); | 3024 set_fpu_register(fd_reg(), kFPU64InvalidResult); |
3372 } | 3025 } |
3373 } else { | 3026 } else { |
3374 UNSUPPORTED(); | 3027 UNSUPPORTED(); |
3375 } | 3028 } |
3376 break; | 3029 break; |
3377 } | 3030 } |
3378 case MIN: | 3031 case MIN: |
3379 DCHECK(IsMipsArchVariant(kMips32r6)); | 3032 DCHECK(IsMipsArchVariant(kMips32r6)); |
3380 fs = get_fpu_register_float(fs_reg); | 3033 fs = get_fpu_register_float(fs_reg()); |
3381 if (std::isnan(fs) && std::isnan(ft)) { | 3034 if (std::isnan(fs) && std::isnan(ft)) { |
3382 set_fpu_register_float(fd_reg, fs); | 3035 set_fpu_register_float(fd_reg(), fs); |
3383 } else if (std::isnan(fs) && !std::isnan(ft)) { | 3036 } else if (std::isnan(fs) && !std::isnan(ft)) { |
3384 set_fpu_register_float(fd_reg, ft); | 3037 set_fpu_register_float(fd_reg(), ft); |
3385 } else if (!std::isnan(fs) && std::isnan(ft)) { | 3038 } else if (!std::isnan(fs) && std::isnan(ft)) { |
3386 set_fpu_register_float(fd_reg, fs); | 3039 set_fpu_register_float(fd_reg(), fs); |
3387 } else { | 3040 } else { |
3388 set_fpu_register_float(fd_reg, (fs >= ft) ? ft : fs); | 3041 set_fpu_register_float(fd_reg(), (fs >= ft) ? ft : fs); |
3389 } | 3042 } |
3390 break; | 3043 break; |
3391 case MAX: | 3044 case MAX: |
3392 DCHECK(IsMipsArchVariant(kMips32r6)); | 3045 DCHECK(IsMipsArchVariant(kMips32r6)); |
3393 fs = get_fpu_register_float(fs_reg); | 3046 fs = get_fpu_register_float(fs_reg()); |
3394 if (std::isnan(fs) && std::isnan(ft)) { | 3047 if (std::isnan(fs) && std::isnan(ft)) { |
3395 set_fpu_register_float(fd_reg, fs); | 3048 set_fpu_register_float(fd_reg(), fs); |
3396 } else if (std::isnan(fs) && !std::isnan(ft)) { | 3049 } else if (std::isnan(fs) && !std::isnan(ft)) { |
3397 set_fpu_register_float(fd_reg, ft); | 3050 set_fpu_register_float(fd_reg(), ft); |
3398 } else if (!std::isnan(fs) && std::isnan(ft)) { | 3051 } else if (!std::isnan(fs) && std::isnan(ft)) { |
3399 set_fpu_register_float(fd_reg, fs); | 3052 set_fpu_register_float(fd_reg(), fs); |
3400 } else { | 3053 } else { |
3401 set_fpu_register_float(fd_reg, (fs <= ft) ? ft : fs); | 3054 set_fpu_register_float(fd_reg(), (fs <= ft) ? ft : fs); |
3402 } | 3055 } |
3403 break; | 3056 break; |
3404 case MINA: | 3057 case MINA: |
3405 DCHECK(IsMipsArchVariant(kMips32r6)); | 3058 DCHECK(IsMipsArchVariant(kMips32r6)); |
3406 fs = get_fpu_register_float(fs_reg); | 3059 fs = get_fpu_register_float(fs_reg()); |
3407 if (std::isnan(fs) && std::isnan(ft)) { | 3060 if (std::isnan(fs) && std::isnan(ft)) { |
3408 set_fpu_register_float(fd_reg, fs); | 3061 set_fpu_register_float(fd_reg(), fs); |
3409 } else if (std::isnan(fs) && !std::isnan(ft)) { | 3062 } else if (std::isnan(fs) && !std::isnan(ft)) { |
3410 set_fpu_register_float(fd_reg, ft); | 3063 set_fpu_register_float(fd_reg(), ft); |
3411 } else if (!std::isnan(fs) && std::isnan(ft)) { | 3064 } else if (!std::isnan(fs) && std::isnan(ft)) { |
3412 set_fpu_register_float(fd_reg, fs); | 3065 set_fpu_register_float(fd_reg(), fs); |
3413 } else { | 3066 } else { |
3414 float result; | 3067 float result; |
3415 if (fabs(fs) > fabs(ft)) { | 3068 if (fabs(fs) > fabs(ft)) { |
3416 result = ft; | 3069 result = ft; |
3417 } else if (fabs(fs) < fabs(ft)) { | 3070 } else if (fabs(fs) < fabs(ft)) { |
3418 result = fs; | 3071 result = fs; |
3419 } else { | 3072 } else { |
3420 result = (fs > ft ? fs : ft); | 3073 result = (fs > ft ? fs : ft); |
3421 } | 3074 } |
3422 set_fpu_register_float(fd_reg, result); | 3075 set_fpu_register_float(fd_reg(), result); |
3423 } | 3076 } |
3424 break; | 3077 break; |
3425 case MAXA: | 3078 case MAXA: |
3426 DCHECK(IsMipsArchVariant(kMips32r6)); | 3079 DCHECK(IsMipsArchVariant(kMips32r6)); |
3427 fs = get_fpu_register_float(fs_reg); | 3080 fs = get_fpu_register_float(fs_reg()); |
3428 if (std::isnan(fs) && std::isnan(ft)) { | 3081 if (std::isnan(fs) && std::isnan(ft)) { |
3429 set_fpu_register_float(fd_reg, fs); | 3082 set_fpu_register_float(fd_reg(), fs); |
3430 } else if (std::isnan(fs) && !std::isnan(ft)) { | 3083 } else if (std::isnan(fs) && !std::isnan(ft)) { |
3431 set_fpu_register_float(fd_reg, ft); | 3084 set_fpu_register_float(fd_reg(), ft); |
3432 } else if (!std::isnan(fs) && std::isnan(ft)) { | 3085 } else if (!std::isnan(fs) && std::isnan(ft)) { |
3433 set_fpu_register_float(fd_reg, fs); | 3086 set_fpu_register_float(fd_reg(), fs); |
3434 } else { | 3087 } else { |
3435 float result; | 3088 float result; |
3436 if (fabs(fs) < fabs(ft)) { | 3089 if (fabs(fs) < fabs(ft)) { |
3437 result = ft; | 3090 result = ft; |
3438 } else if (fabs(fs) > fabs(ft)) { | 3091 } else if (fabs(fs) > fabs(ft)) { |
3439 result = fs; | 3092 result = fs; |
3440 } else { | 3093 } else { |
3441 result = (fs > ft ? fs : ft); | 3094 result = (fs > ft ? fs : ft); |
3442 } | 3095 } |
3443 set_fpu_register_float(fd_reg, result); | 3096 set_fpu_register_float(fd_reg(), result); |
3444 } | 3097 } |
3445 break; | 3098 break; |
3446 case CVT_L_S: { | 3099 case CVT_L_S: { |
3447 if (IsFp64Mode()) { | 3100 if (IsFp64Mode()) { |
3448 int64_t result; | 3101 int64_t result; |
3449 float rounded; | 3102 float rounded; |
3450 round64_according_to_fcsr(fs, rounded, result, fs); | 3103 round64_according_to_fcsr(fs, rounded, result, fs); |
3451 set_fpu_register(fd_reg, result); | 3104 set_fpu_register(fd_reg(), result); |
3452 if (set_fcsr_round64_error(fs, rounded)) { | 3105 if (set_fcsr_round64_error(fs, rounded)) { |
3453 set_fpu_register(fd_reg, kFPU64InvalidResult); | 3106 set_fpu_register(fd_reg(), kFPU64InvalidResult); |
3454 } | 3107 } |
3455 } else { | 3108 } else { |
3456 UNSUPPORTED(); | 3109 UNSUPPORTED(); |
3457 } | 3110 } |
3458 break; | 3111 break; |
3459 } | 3112 } |
3460 case CVT_W_S: { | 3113 case CVT_W_S: { |
3461 float rounded; | 3114 float rounded; |
3462 int32_t result; | 3115 int32_t result; |
3463 round_according_to_fcsr(fs, rounded, result, fs); | 3116 round_according_to_fcsr(fs, rounded, result, fs); |
3464 set_fpu_register_word(fd_reg, result); | 3117 set_fpu_register_word(fd_reg(), result); |
3465 if (set_fcsr_round_error(fs, rounded)) { | 3118 if (set_fcsr_round_error(fs, rounded)) { |
3466 set_fpu_register_word(fd_reg, kFPUInvalidResult); | 3119 set_fpu_register_word(fd_reg(), kFPUInvalidResult); |
3467 } | 3120 } |
3468 break; | 3121 break; |
3469 } | 3122 } |
3470 default: | 3123 default: |
3471 // CVT_W_S CVT_L_S ROUND_W_S ROUND_L_S FLOOR_W_S FLOOR_L_S | 3124 // CVT_W_S CVT_L_S ROUND_W_S ROUND_L_S FLOOR_W_S FLOOR_L_S |
3472 // CEIL_W_S CEIL_L_S CVT_PS_S are unimplemented. | 3125 // CEIL_W_S CEIL_L_S CVT_PS_S are unimplemented. |
3473 UNREACHABLE(); | 3126 UNREACHABLE(); |
3474 } | 3127 } |
3475 } | 3128 } |
3476 | 3129 |
3477 | 3130 |
3478 void Simulator::DecodeTypeRegisterLRsType(Instruction* instr, | 3131 void Simulator::DecodeTypeRegisterLRsType() { |
3479 const int32_t& ft_reg, | 3132 double fs = get_fpu_register_double(fs_reg()); |
3480 const int32_t& fs_reg, | 3133 double ft = get_fpu_register_double(ft_reg()); |
3481 const int32_t& fd_reg) { | 3134 switch (get_instr()->FunctionFieldRaw()) { |
3482 double fs = get_fpu_register_double(fs_reg); | |
3483 double ft = get_fpu_register_double(ft_reg); | |
3484 switch (instr->FunctionFieldRaw()) { | |
3485 case CVT_D_L: // Mips32r2 instruction. | 3135 case CVT_D_L: // Mips32r2 instruction. |
3486 // Watch the signs here, we want 2 32-bit vals | 3136 // Watch the signs here, we want 2 32-bit vals |
3487 // to make a sign-64. | 3137 // to make a sign-64. |
3488 int64_t i64; | 3138 int64_t i64; |
3489 if (IsFp64Mode()) { | 3139 if (IsFp64Mode()) { |
3490 i64 = get_fpu_register(fs_reg); | 3140 i64 = get_fpu_register(fs_reg()); |
3491 } else { | 3141 } else { |
3492 i64 = static_cast<uint32_t>(get_fpu_register_word(fs_reg)); | 3142 i64 = static_cast<uint32_t>(get_fpu_register_word(fs_reg())); |
3493 i64 |= static_cast<int64_t>(get_fpu_register_word(fs_reg + 1)) << 32; | 3143 i64 |= static_cast<int64_t>(get_fpu_register_word(fs_reg() + 1)) << 32; |
3494 } | 3144 } |
3495 set_fpu_register_double(fd_reg, static_cast<double>(i64)); | 3145 set_fpu_register_double(fd_reg(), static_cast<double>(i64)); |
3496 break; | 3146 break; |
3497 case CVT_S_L: | 3147 case CVT_S_L: |
3498 if (IsFp64Mode()) { | 3148 if (IsFp64Mode()) { |
3499 i64 = get_fpu_register(fs_reg); | 3149 i64 = get_fpu_register(fs_reg()); |
3500 } else { | 3150 } else { |
3501 i64 = static_cast<uint32_t>(get_fpu_register_word(fs_reg)); | 3151 i64 = static_cast<uint32_t>(get_fpu_register_word(fs_reg())); |
3502 i64 |= static_cast<int64_t>(get_fpu_register_word(fs_reg + 1)) << 32; | 3152 i64 |= static_cast<int64_t>(get_fpu_register_word(fs_reg() + 1)) << 32; |
3503 } | 3153 } |
3504 set_fpu_register_float(fd_reg, static_cast<float>(i64)); | 3154 set_fpu_register_float(fd_reg(), static_cast<float>(i64)); |
3505 break; | 3155 break; |
3506 case CMP_AF: // Mips64r6 CMP.D instructions. | 3156 case CMP_AF: // Mips64r6 CMP.D instructions. |
3507 set_fpu_register(fd_reg, 0); | 3157 set_fpu_register(fd_reg(), 0); |
3508 break; | 3158 break; |
3509 case CMP_UN: | 3159 case CMP_UN: |
3510 if (std::isnan(fs) || std::isnan(ft)) { | 3160 if (std::isnan(fs) || std::isnan(ft)) { |
3511 set_fpu_register(fd_reg, -1); | 3161 set_fpu_register(fd_reg(), -1); |
3512 } else { | 3162 } else { |
3513 set_fpu_register(fd_reg, 0); | 3163 set_fpu_register(fd_reg(), 0); |
3514 } | 3164 } |
3515 break; | 3165 break; |
3516 case CMP_EQ: | 3166 case CMP_EQ: |
3517 if (fs == ft) { | 3167 if (fs == ft) { |
3518 set_fpu_register(fd_reg, -1); | 3168 set_fpu_register(fd_reg(), -1); |
3519 } else { | 3169 } else { |
3520 set_fpu_register(fd_reg, 0); | 3170 set_fpu_register(fd_reg(), 0); |
3521 } | 3171 } |
3522 break; | 3172 break; |
3523 case CMP_UEQ: | 3173 case CMP_UEQ: |
3524 if ((fs == ft) || (std::isnan(fs) || std::isnan(ft))) { | 3174 if ((fs == ft) || (std::isnan(fs) || std::isnan(ft))) { |
3525 set_fpu_register(fd_reg, -1); | 3175 set_fpu_register(fd_reg(), -1); |
3526 } else { | 3176 } else { |
3527 set_fpu_register(fd_reg, 0); | 3177 set_fpu_register(fd_reg(), 0); |
3528 } | 3178 } |
3529 break; | 3179 break; |
3530 case CMP_LT: | 3180 case CMP_LT: |
3531 if (fs < ft) { | 3181 if (fs < ft) { |
3532 set_fpu_register(fd_reg, -1); | 3182 set_fpu_register(fd_reg(), -1); |
3533 } else { | 3183 } else { |
3534 set_fpu_register(fd_reg, 0); | 3184 set_fpu_register(fd_reg(), 0); |
3535 } | 3185 } |
3536 break; | 3186 break; |
3537 case CMP_ULT: | 3187 case CMP_ULT: |
3538 if ((fs < ft) || (std::isnan(fs) || std::isnan(ft))) { | 3188 if ((fs < ft) || (std::isnan(fs) || std::isnan(ft))) { |
3539 set_fpu_register(fd_reg, -1); | 3189 set_fpu_register(fd_reg(), -1); |
3540 } else { | 3190 } else { |
3541 set_fpu_register(fd_reg, 0); | 3191 set_fpu_register(fd_reg(), 0); |
3542 } | 3192 } |
3543 break; | 3193 break; |
3544 case CMP_LE: | 3194 case CMP_LE: |
3545 if (fs <= ft) { | 3195 if (fs <= ft) { |
3546 set_fpu_register(fd_reg, -1); | 3196 set_fpu_register(fd_reg(), -1); |
3547 } else { | 3197 } else { |
3548 set_fpu_register(fd_reg, 0); | 3198 set_fpu_register(fd_reg(), 0); |
3549 } | 3199 } |
3550 break; | 3200 break; |
3551 case CMP_ULE: | 3201 case CMP_ULE: |
3552 if ((fs <= ft) || (std::isnan(fs) || std::isnan(ft))) { | 3202 if ((fs <= ft) || (std::isnan(fs) || std::isnan(ft))) { |
3553 set_fpu_register(fd_reg, -1); | 3203 set_fpu_register(fd_reg(), -1); |
3554 } else { | 3204 } else { |
3555 set_fpu_register(fd_reg, 0); | 3205 set_fpu_register(fd_reg(), 0); |
3556 } | 3206 } |
3557 break; | 3207 break; |
3558 case CMP_OR: | 3208 case CMP_OR: |
3559 if (!std::isnan(fs) && !std::isnan(ft)) { | 3209 if (!std::isnan(fs) && !std::isnan(ft)) { |
3560 set_fpu_register(fd_reg, -1); | 3210 set_fpu_register(fd_reg(), -1); |
3561 } else { | 3211 } else { |
3562 set_fpu_register(fd_reg, 0); | 3212 set_fpu_register(fd_reg(), 0); |
3563 } | 3213 } |
3564 break; | 3214 break; |
3565 case CMP_UNE: | 3215 case CMP_UNE: |
3566 if ((fs != ft) || (std::isnan(fs) || std::isnan(ft))) { | 3216 if ((fs != ft) || (std::isnan(fs) || std::isnan(ft))) { |
3567 set_fpu_register(fd_reg, -1); | 3217 set_fpu_register(fd_reg(), -1); |
3568 } else { | 3218 } else { |
3569 set_fpu_register(fd_reg, 0); | 3219 set_fpu_register(fd_reg(), 0); |
3570 } | 3220 } |
3571 break; | 3221 break; |
3572 case CMP_NE: | 3222 case CMP_NE: |
3573 if (fs != ft && (!std::isnan(fs) && !std::isnan(ft))) { | 3223 if (fs != ft && (!std::isnan(fs) && !std::isnan(ft))) { |
3574 set_fpu_register(fd_reg, -1); | 3224 set_fpu_register(fd_reg(), -1); |
3575 } else { | 3225 } else { |
3576 set_fpu_register(fd_reg, 0); | 3226 set_fpu_register(fd_reg(), 0); |
3577 } | 3227 } |
3578 break; | 3228 break; |
3579 default: | 3229 default: |
3580 UNREACHABLE(); | 3230 UNREACHABLE(); |
3581 } | 3231 } |
3582 } | 3232 } |
3583 | 3233 |
3584 | 3234 |
3585 void Simulator::DecodeTypeRegisterCOP1( | 3235 void Simulator::DecodeTypeRegisterCOP1() { |
3586 Instruction* instr, const int32_t& rs_reg, const int32_t& rs, | 3236 switch (get_instr()->RsFieldRaw()) { |
3587 const uint32_t& rs_u, const int32_t& rt_reg, const int32_t& rt, | |
3588 const uint32_t& rt_u, const int32_t& rd_reg, const int32_t& fr_reg, | |
3589 const int32_t& fs_reg, const int32_t& ft_reg, const int32_t& fd_reg, | |
3590 int64_t& i64hilo, uint64_t& u64hilo, int32_t& alu_out, bool& do_interrupt, | |
3591 int32_t& current_pc, int32_t& next_pc, int32_t& return_addr_reg) { | |
3592 switch (instr->RsFieldRaw()) { | |
3593 case CFC1: | 3237 case CFC1: |
3594 set_register(rt_reg, alu_out); | 3238 // At the moment only FCSR is supported. |
| 3239 DCHECK(fs_reg() == kFCSRRegister); |
| 3240 set_register(rt_reg(), FCSR_); |
3595 break; | 3241 break; |
3596 case MFC1: | 3242 case MFC1: |
3597 set_register(rt_reg, alu_out); | 3243 set_register(rt_reg(), get_fpu_register_word(fs_reg())); |
3598 break; | 3244 break; |
3599 case MFHC1: | 3245 case MFHC1: |
3600 set_register(rt_reg, alu_out); | 3246 set_register(rt_reg(), get_fpu_register_hi_word(fs_reg())); |
3601 break; | 3247 break; |
3602 case CTC1: | 3248 case CTC1: |
3603 // At the moment only FCSR is supported. | 3249 // At the moment only FCSR is supported. |
3604 DCHECK(fs_reg == kFCSRRegister); | 3250 DCHECK(fs_reg() == kFCSRRegister); |
3605 FCSR_ = registers_[rt_reg]; | 3251 FCSR_ = registers_[rt_reg()]; |
3606 break; | 3252 break; |
3607 case MTC1: | 3253 case MTC1: |
3608 // Hardware writes upper 32-bits to zero on mtc1. | 3254 // Hardware writes upper 32-bits to zero on mtc1. |
3609 set_fpu_register_hi_word(fs_reg, 0); | 3255 set_fpu_register_hi_word(fs_reg(), 0); |
3610 set_fpu_register_word(fs_reg, registers_[rt_reg]); | 3256 set_fpu_register_word(fs_reg(), registers_[rt_reg()]); |
3611 break; | 3257 break; |
3612 case MTHC1: | 3258 case MTHC1: |
3613 set_fpu_register_hi_word(fs_reg, registers_[rt_reg]); | 3259 set_fpu_register_hi_word(fs_reg(), registers_[rt_reg()]); |
3614 break; | 3260 break; |
3615 case S: { | 3261 case S: { |
3616 DecodeTypeRegisterSRsType(instr, ft_reg, fs_reg, fd_reg); | 3262 DecodeTypeRegisterSRsType(); |
3617 break; | 3263 break; |
3618 } | 3264 } |
3619 case D: | 3265 case D: |
3620 DecodeTypeRegisterDRsType(instr, fr_reg, fs_reg, ft_reg, fd_reg); | 3266 DecodeTypeRegisterDRsType(); |
3621 break; | 3267 break; |
3622 case W: | 3268 case W: |
3623 DecodeTypeRegisterWRsType(instr, alu_out, fd_reg, fs_reg, ft_reg); | 3269 DecodeTypeRegisterWRsType(); |
3624 break; | 3270 break; |
3625 case L: | 3271 case L: |
3626 DecodeTypeRegisterLRsType(instr, ft_reg, fs_reg, fd_reg); | 3272 DecodeTypeRegisterLRsType(); |
3627 break; | 3273 break; |
| 3274 case PS: |
| 3275 // Not implemented. |
| 3276 UNREACHABLE(); |
3628 default: | 3277 default: |
3629 UNREACHABLE(); | 3278 UNREACHABLE(); |
3630 } | 3279 } |
3631 } | 3280 } |
3632 | 3281 |
3633 | 3282 |
3634 void Simulator::DecodeTypeRegisterCOP1X(Instruction* instr, | 3283 void Simulator::DecodeTypeRegisterCOP1X() { |
3635 const int32_t& fr_reg, | 3284 switch (get_instr()->FunctionFieldRaw()) { |
3636 const int32_t& fs_reg, | |
3637 const int32_t& ft_reg, | |
3638 const int32_t& fd_reg) { | |
3639 switch (instr->FunctionFieldRaw()) { | |
3640 case MADD_D: | 3285 case MADD_D: |
3641 double fr, ft, fs; | 3286 double fr, ft, fs; |
3642 fr = get_fpu_register_double(fr_reg); | 3287 fr = get_fpu_register_double(fr_reg()); |
3643 fs = get_fpu_register_double(fs_reg); | 3288 fs = get_fpu_register_double(fs_reg()); |
3644 ft = get_fpu_register_double(ft_reg); | 3289 ft = get_fpu_register_double(ft_reg()); |
3645 set_fpu_register_double(fd_reg, fs * ft + fr); | 3290 set_fpu_register_double(fd_reg(), fs * ft + fr); |
3646 break; | 3291 break; |
3647 default: | 3292 default: |
3648 UNREACHABLE(); | 3293 UNREACHABLE(); |
3649 } | 3294 } |
3650 } | 3295 } |
3651 | 3296 |
3652 | 3297 |
3653 void Simulator::DecodeTypeRegisterSPECIAL( | 3298 void Simulator::DecodeTypeRegisterSPECIAL() { |
3654 Instruction* instr, const int32_t& rs_reg, const int32_t& rs, | 3299 int64_t alu_out = 0x12345678; |
3655 const uint32_t& rs_u, const int32_t& rt_reg, const int32_t& rt, | 3300 int64_t i64hilo = 0; |
3656 const uint32_t& rt_u, const int32_t& rd_reg, const int32_t& fr_reg, | 3301 uint64_t u64hilo = 0; |
3657 const int32_t& fs_reg, const int32_t& ft_reg, const int32_t& fd_reg, | 3302 bool do_interrupt = false; |
3658 int64_t& i64hilo, uint64_t& u64hilo, int32_t& alu_out, bool& do_interrupt, | 3303 |
3659 int32_t& current_pc, int32_t& next_pc, int32_t& return_addr_reg) { | 3304 switch (get_instr()->FunctionFieldRaw()) { |
3660 switch (instr->FunctionFieldRaw()) { | |
3661 case SELEQZ_S: | 3305 case SELEQZ_S: |
3662 DCHECK(IsMipsArchVariant(kMips32r6)); | 3306 DCHECK(IsMipsArchVariant(kMips32r6)); |
3663 set_register(rd_reg, rt == 0 ? rs : 0); | 3307 set_register(rd_reg(), rt() == 0 ? rs() : 0); |
3664 break; | 3308 break; |
3665 case SELNEZ_S: | 3309 case SELNEZ_S: |
3666 DCHECK(IsMipsArchVariant(kMips32r6)); | 3310 DCHECK(IsMipsArchVariant(kMips32r6)); |
3667 set_register(rd_reg, rt != 0 ? rs : 0); | 3311 set_register(rd_reg(), rt() != 0 ? rs() : 0); |
3668 break; | 3312 break; |
3669 case JR: { | 3313 case JR: { |
3670 Instruction* branch_delay_instr = reinterpret_cast<Instruction*>( | 3314 int32_t next_pc = rs(); |
3671 current_pc+Instruction::kInstrSize); | 3315 int32_t current_pc = get_pc(); |
3672 BranchDelayInstructionDecode(branch_delay_instr); | 3316 Instruction* branch_delay_instr = |
3673 set_pc(next_pc); | 3317 reinterpret_cast<Instruction*>(current_pc + Instruction::kInstrSize); |
3674 pc_modified_ = true; | 3318 BranchDelayInstructionDecode(branch_delay_instr); |
3675 break; | 3319 set_pc(next_pc); |
3676 } | 3320 pc_modified_ = true; |
3677 case JALR: { | 3321 break; |
3678 Instruction* branch_delay_instr = reinterpret_cast<Instruction*>( | 3322 } |
3679 current_pc+Instruction::kInstrSize); | 3323 case JALR: { |
3680 BranchDelayInstructionDecode(branch_delay_instr); | 3324 int32_t next_pc = rs(); |
3681 set_register(return_addr_reg, | 3325 int32_t return_addr_reg = rd_reg(); |
3682 current_pc + 2 * Instruction::kInstrSize); | 3326 int32_t current_pc = get_pc(); |
3683 set_pc(next_pc); | 3327 Instruction* branch_delay_instr = |
3684 pc_modified_ = true; | 3328 reinterpret_cast<Instruction*>(current_pc + Instruction::kInstrSize); |
3685 break; | 3329 BranchDelayInstructionDecode(branch_delay_instr); |
3686 } | 3330 set_register(return_addr_reg, current_pc + 2 * Instruction::kInstrSize); |
3687 // Instructions using HI and LO registers. | 3331 set_pc(next_pc); |
3688 case MULT: | 3332 pc_modified_ = true; |
3689 if (!IsMipsArchVariant(kMips32r6)) { | 3333 break; |
3690 set_register(LO, static_cast<int32_t>(i64hilo & 0xffffffff)); | 3334 } |
3691 set_register(HI, static_cast<int32_t>(i64hilo >> 32)); | 3335 case SLL: |
3692 } else { | 3336 alu_out = rt() << sa(); |
3693 switch (instr->SaValue()) { | 3337 SetResult(rd_reg(), static_cast<int32_t>(alu_out)); |
3694 case MUL_OP: | 3338 break; |
3695 set_register(rd_reg, | 3339 case SRL: |
3696 static_cast<int32_t>(i64hilo & 0xffffffff)); | 3340 if (rs_reg() == 0) { |
3697 break; | 3341 // Regular logical right shift of a word by a fixed number of |
3698 case MUH_OP: | 3342 // bits instruction. RS field is always equal to 0. |
3699 set_register(rd_reg, static_cast<int32_t>(i64hilo >> 32)); | 3343 alu_out = rt_u() >> sa(); |
3700 break; | 3344 } else { |
3701 default: | 3345 // Logical right-rotate of a word by a fixed number of bits. This |
3702 UNIMPLEMENTED_MIPS(); | 3346 // is special case of SRL instruction, added in MIPS32 Release 2. |
3703 break; | 3347 // RS field is equal to 00001. |
| 3348 alu_out = base::bits::RotateRight32(rt_u(), sa()); |
| 3349 } |
| 3350 SetResult(rd_reg(), static_cast<int32_t>(alu_out)); |
| 3351 break; |
| 3352 case SRA: |
| 3353 alu_out = rt() >> sa(); |
| 3354 SetResult(rd_reg(), static_cast<int32_t>(alu_out)); |
| 3355 break; |
| 3356 case SLLV: |
| 3357 alu_out = rt() << rs(); |
| 3358 SetResult(rd_reg(), static_cast<int32_t>(alu_out)); |
| 3359 break; |
| 3360 case SRLV: |
| 3361 if (sa() == 0) { |
| 3362 // Regular logical right-shift of a word by a variable number of |
| 3363 // bits instruction. SA field is always equal to 0. |
| 3364 alu_out = rt_u() >> rs(); |
| 3365 } else { |
| 3366 // Logical right-rotate of a word by a variable number of bits. |
| 3367 // This is special case od SRLV instruction, added in MIPS32 |
| 3368 // Release 2. SA field is equal to 00001. |
| 3369 alu_out = base::bits::RotateRight32(rt_u(), rs_u()); |
| 3370 } |
| 3371 SetResult(rd_reg(), static_cast<int32_t>(alu_out)); |
| 3372 break; |
| 3373 case SRAV: |
| 3374 alu_out = rt() >> rs(); |
| 3375 SetResult(rd_reg(), static_cast<int32_t>(alu_out)); |
| 3376 break; |
| 3377 case MFHI: // MFHI == CLZ on R6. |
| 3378 if (!IsMipsArchVariant(kMips32r6)) { |
| 3379 DCHECK(sa() == 0); |
| 3380 alu_out = get_register(HI); |
| 3381 } else { |
| 3382 // MIPS spec: If no bits were set in GPR rs, the result written to |
| 3383 // GPR rd is 32. |
| 3384 DCHECK(sa() == 1); |
| 3385 alu_out = base::bits::CountLeadingZeros32(rs_u()); |
| 3386 } |
| 3387 SetResult(rd_reg(), static_cast<int32_t>(alu_out)); |
| 3388 break; |
| 3389 case MFLO: |
| 3390 alu_out = get_register(LO); |
| 3391 SetResult(rd_reg(), static_cast<int32_t>(alu_out)); |
| 3392 break; |
| 3393 // Instructions using HI and LO registers. |
| 3394 case MULT: |
| 3395 i64hilo = static_cast<int64_t>(rs()) * static_cast<int64_t>(rt()); |
| 3396 if (!IsMipsArchVariant(kMips32r6)) { |
| 3397 set_register(LO, static_cast<int32_t>(i64hilo & 0xffffffff)); |
| 3398 set_register(HI, static_cast<int32_t>(i64hilo >> 32)); |
| 3399 } else { |
| 3400 switch (sa()) { |
| 3401 case MUL_OP: |
| 3402 set_register(rd_reg(), static_cast<int32_t>(i64hilo & 0xffffffff)); |
| 3403 break; |
| 3404 case MUH_OP: |
| 3405 set_register(rd_reg(), static_cast<int32_t>(i64hilo >> 32)); |
| 3406 break; |
| 3407 default: |
| 3408 UNIMPLEMENTED_MIPS(); |
| 3409 break; |
| 3410 } |
| 3411 } |
| 3412 break; |
| 3413 case MULTU: |
| 3414 u64hilo = static_cast<uint64_t>(rs_u()) * static_cast<uint64_t>(rt_u()); |
| 3415 if (!IsMipsArchVariant(kMips32r6)) { |
| 3416 set_register(LO, static_cast<int32_t>(u64hilo & 0xffffffff)); |
| 3417 set_register(HI, static_cast<int32_t>(u64hilo >> 32)); |
| 3418 } else { |
| 3419 switch (sa()) { |
| 3420 case MUL_OP: |
| 3421 set_register(rd_reg(), static_cast<int32_t>(u64hilo & 0xffffffff)); |
| 3422 break; |
| 3423 case MUH_OP: |
| 3424 set_register(rd_reg(), static_cast<int32_t>(u64hilo >> 32)); |
| 3425 break; |
| 3426 default: |
| 3427 UNIMPLEMENTED_MIPS(); |
| 3428 break; |
| 3429 } |
| 3430 } |
| 3431 break; |
| 3432 case DIV: |
| 3433 if (IsMipsArchVariant(kMips32r6)) { |
| 3434 switch (get_instr()->SaValue()) { |
| 3435 case DIV_OP: |
| 3436 if (rs() == INT_MIN && rt() == -1) { |
| 3437 set_register(rd_reg(), INT_MIN); |
| 3438 } else if (rt() != 0) { |
| 3439 set_register(rd_reg(), rs() / rt()); |
3704 } | 3440 } |
3705 } | 3441 break; |
3706 break; | 3442 case MOD_OP: |
3707 case MULTU: | 3443 if (rs() == INT_MIN && rt() == -1) { |
3708 if (!IsMipsArchVariant(kMips32r6)) { | 3444 set_register(rd_reg(), 0); |
3709 set_register(LO, static_cast<int32_t>(u64hilo & 0xffffffff)); | 3445 } else if (rt() != 0) { |
3710 set_register(HI, static_cast<int32_t>(u64hilo >> 32)); | 3446 set_register(rd_reg(), rs() % rt()); |
3711 } else { | |
3712 switch (instr->SaValue()) { | |
3713 case MUL_OP: | |
3714 set_register(rd_reg, | |
3715 static_cast<int32_t>(u64hilo & 0xffffffff)); | |
3716 break; | |
3717 case MUH_OP: | |
3718 set_register(rd_reg, static_cast<int32_t>(u64hilo >> 32)); | |
3719 break; | |
3720 default: | |
3721 UNIMPLEMENTED_MIPS(); | |
3722 break; | |
3723 } | 3447 } |
3724 } | 3448 break; |
3725 break; | 3449 default: |
3726 case DIV: | 3450 UNIMPLEMENTED_MIPS(); |
3727 if (IsMipsArchVariant(kMips32r6)) { | 3451 break; |
3728 switch (instr->SaValue()) { | 3452 } |
3729 case DIV_OP: | 3453 } else { |
3730 if (rs == INT_MIN && rt == -1) { | 3454 // Divide by zero and overflow was not checked in the |
3731 set_register(rd_reg, INT_MIN); | 3455 // configuration step - div and divu do not raise exceptions. On |
3732 } else if (rt != 0) { | 3456 // division by 0 the result will be UNPREDICTABLE. On overflow |
3733 set_register(rd_reg, rs / rt); | 3457 // (INT_MIN/-1), return INT_MIN which is what the hardware does. |
3734 } | 3458 if (rs() == INT_MIN && rt() == -1) { |
3735 break; | 3459 set_register(LO, INT_MIN); |
3736 case MOD_OP: | 3460 set_register(HI, 0); |
3737 if (rs == INT_MIN && rt == -1) { | 3461 } else if (rt() != 0) { |
3738 set_register(rd_reg, 0); | 3462 set_register(LO, rs() / rt()); |
3739 } else if (rt != 0) { | 3463 set_register(HI, rs() % rt()); |
3740 set_register(rd_reg, rs % rt); | 3464 } |
3741 } | 3465 } |
3742 break; | 3466 break; |
3743 default: | 3467 case DIVU: |
3744 UNIMPLEMENTED_MIPS(); | 3468 if (IsMipsArchVariant(kMips32r6)) { |
3745 break; | 3469 switch (get_instr()->SaValue()) { |
| 3470 case DIV_OP: |
| 3471 if (rt_u() != 0) { |
| 3472 set_register(rd_reg(), rs_u() / rt_u()); |
3746 } | 3473 } |
3747 } else { | 3474 break; |
3748 // Divide by zero and overflow was not checked in the | 3475 case MOD_OP: |
3749 // configuration step - div and divu do not raise exceptions. On | 3476 if (rt_u() != 0) { |
3750 // division by 0 the result will be UNPREDICTABLE. On overflow | 3477 set_register(rd_reg(), rs_u() % rt_u()); |
3751 // (INT_MIN/-1), return INT_MIN which is what the hardware does. | |
3752 if (rs == INT_MIN && rt == -1) { | |
3753 set_register(LO, INT_MIN); | |
3754 set_register(HI, 0); | |
3755 } else if (rt != 0) { | |
3756 set_register(LO, rs / rt); | |
3757 set_register(HI, rs % rt); | |
3758 } | 3478 } |
3759 } | 3479 break; |
3760 break; | 3480 default: |
3761 case DIVU: | 3481 UNIMPLEMENTED_MIPS(); |
3762 if (IsMipsArchVariant(kMips32r6)) { | 3482 break; |
3763 switch (instr->SaValue()) { | 3483 } |
3764 case DIV_OP: | 3484 } else { |
3765 if (rt_u != 0) { | 3485 if (rt_u() != 0) { |
3766 set_register(rd_reg, rs_u / rt_u); | 3486 set_register(LO, rs_u() / rt_u()); |
3767 } | 3487 set_register(HI, rs_u() % rt_u()); |
3768 break; | 3488 } |
3769 case MOD_OP: | 3489 } |
3770 if (rt_u != 0) { | 3490 break; |
3771 set_register(rd_reg, rs_u % rt_u); | 3491 case ADD: |
3772 } | 3492 if (HaveSameSign(rs(), rt())) { |
3773 break; | 3493 if (rs() > 0) { |
3774 default: | 3494 if (rs() <= (Registers::kMaxValue - rt())) { |
3775 UNIMPLEMENTED_MIPS(); | 3495 SignalException(kIntegerOverflow); |
3776 break; | 3496 } |
3777 } | 3497 } else if (rs() < 0) { |
3778 } else { | 3498 if (rs() >= (Registers::kMinValue - rt())) { |
3779 if (rt_u != 0) { | 3499 SignalException(kIntegerUnderflow); |
3780 set_register(LO, rs_u / rt_u); | 3500 } |
3781 set_register(HI, rs_u % rt_u); | 3501 } |
3782 } | 3502 } |
3783 } | 3503 SetResult(rd_reg(), rs() + rt()); |
3784 break; | 3504 break; |
3785 // Break and trap instructions. | 3505 case ADDU: |
3786 case BREAK: | 3506 SetResult(rd_reg(), rs() + rt()); |
3787 case TGE: | 3507 break; |
3788 case TGEU: | 3508 case SUB: |
3789 case TLT: | 3509 if (!HaveSameSign(rs(), rt())) { |
3790 case TLTU: | 3510 if (rs() > 0) { |
3791 case TEQ: | 3511 if (rs() <= (Registers::kMaxValue + rt())) { |
3792 case TNE: | 3512 SignalException(kIntegerOverflow); |
3793 if (do_interrupt) { | 3513 } |
3794 SoftwareInterrupt(instr); | 3514 } else if (rs() < 0) { |
3795 } | 3515 if (rs() >= (Registers::kMinValue + rt())) { |
3796 break; | 3516 SignalException(kIntegerUnderflow); |
3797 // Conditional moves. | 3517 } |
3798 case MOVN: | 3518 } |
3799 if (rt) { | 3519 } |
3800 set_register(rd_reg, rs); | 3520 SetResult(rd_reg(), rs() - rt()); |
3801 TraceRegWr(rs); | 3521 break; |
3802 } | 3522 case SUBU: |
3803 break; | 3523 SetResult(rd_reg(), rs() - rt()); |
3804 case MOVCI: { | 3524 break; |
3805 uint32_t cc = instr->FBccValue(); | 3525 case AND: |
3806 uint32_t fcsr_cc = get_fcsr_condition_bit(cc); | 3526 SetResult(rd_reg(), rs() & rt()); |
3807 if (instr->Bit(16)) { // Read Tf bit. | 3527 break; |
3808 if (test_fcsr_bit(fcsr_cc)) set_register(rd_reg, rs); | 3528 case OR: |
3809 } else { | 3529 SetResult(rd_reg(), rs() | rt()); |
3810 if (!test_fcsr_bit(fcsr_cc)) set_register(rd_reg, rs); | 3530 break; |
3811 } | 3531 case XOR: |
3812 break; | 3532 SetResult(rd_reg(), rs() ^ rt()); |
3813 } | 3533 break; |
3814 case MOVZ: | 3534 case NOR: |
3815 if (!rt) { | 3535 SetResult(rd_reg(), ~(rs() | rt())); |
3816 set_register(rd_reg, rs); | 3536 break; |
3817 TraceRegWr(rs); | 3537 case SLT: |
3818 } | 3538 SetResult(rd_reg(), rs() < rt() ? 1 : 0); |
3819 break; | 3539 break; |
3820 default: // For other special opcodes we do the default operation. | 3540 case SLTU: |
3821 set_register(rd_reg, alu_out); | 3541 SetResult(rd_reg(), rs_u() < rt_u() ? 1 : 0); |
3822 TraceRegWr(alu_out); | 3542 break; |
3823 } | 3543 // Break and trap instructions. |
| 3544 case BREAK: |
| 3545 do_interrupt = true; |
| 3546 break; |
| 3547 case TGE: |
| 3548 do_interrupt = rs() >= rt(); |
| 3549 break; |
| 3550 case TGEU: |
| 3551 do_interrupt = rs_u() >= rt_u(); |
| 3552 break; |
| 3553 case TLT: |
| 3554 do_interrupt = rs() < rt(); |
| 3555 break; |
| 3556 case TLTU: |
| 3557 do_interrupt = rs_u() < rt_u(); |
| 3558 break; |
| 3559 case TEQ: |
| 3560 do_interrupt = rs() == rt(); |
| 3561 break; |
| 3562 case TNE: |
| 3563 do_interrupt = rs() != rt(); |
| 3564 break; |
| 3565 // Conditional moves. |
| 3566 case MOVN: |
| 3567 if (rt()) { |
| 3568 set_register(rd_reg(), rs()); |
| 3569 TraceRegWr(rs()); |
| 3570 } |
| 3571 break; |
| 3572 case MOVCI: { |
| 3573 uint32_t cc = get_instr()->FBccValue(); |
| 3574 uint32_t fcsr_cc = get_fcsr_condition_bit(cc); |
| 3575 if (get_instr()->Bit(16)) { // Read Tf bit. |
| 3576 if (test_fcsr_bit(fcsr_cc)) set_register(rd_reg(), rs()); |
| 3577 } else { |
| 3578 if (!test_fcsr_bit(fcsr_cc)) set_register(rd_reg(), rs()); |
| 3579 } |
| 3580 break; |
| 3581 } |
| 3582 case MOVZ: |
| 3583 if (!rt()) { |
| 3584 set_register(rd_reg(), rs()); |
| 3585 TraceRegWr(rs()); |
| 3586 } |
| 3587 break; |
| 3588 default: |
| 3589 UNREACHABLE(); |
| 3590 } |
| 3591 if (do_interrupt) { |
| 3592 SoftwareInterrupt(get_instr()); |
| 3593 } |
3824 } | 3594 } |
3825 | 3595 |
3826 | 3596 |
3827 void Simulator::DecodeTypeRegisterSPECIAL2(Instruction* instr, | 3597 void Simulator::DecodeTypeRegisterSPECIAL2() { |
3828 const int32_t& rd_reg, | 3598 int32_t alu_out; |
3829 int32_t& alu_out) { | 3599 switch (get_instr()->FunctionFieldRaw()) { |
3830 switch (instr->FunctionFieldRaw()) { | |
3831 case MUL: | 3600 case MUL: |
3832 set_register(rd_reg, alu_out); | 3601 // Only the lower 32 bits are kept. |
3833 TraceRegWr(alu_out); | 3602 alu_out = rs_u() * rt_u(); |
3834 // HI and LO are UNPREDICTABLE after the operation. | 3603 // HI and LO are UNPREDICTABLE after the operation. |
3835 set_register(LO, Unpredictable); | 3604 set_register(LO, Unpredictable); |
3836 set_register(HI, Unpredictable); | 3605 set_register(HI, Unpredictable); |
3837 break; | 3606 break; |
3838 default: // For other special2 opcodes we do the default operation. | 3607 case CLZ: |
3839 set_register(rd_reg, alu_out); | 3608 // MIPS32 spec: If no bits were set in GPR rs, the result written to |
3840 TraceRegWr(alu_out); | 3609 // GPR rd is 32. |
| 3610 alu_out = base::bits::CountLeadingZeros32(rs_u()); |
| 3611 break; |
| 3612 default: |
| 3613 alu_out = 0x12345678; |
| 3614 UNREACHABLE(); |
3841 } | 3615 } |
| 3616 SetResult(rd_reg(), alu_out); |
3842 } | 3617 } |
3843 | 3618 |
3844 | 3619 |
3845 void Simulator::DecodeTypeRegisterSPECIAL3(Instruction* instr, | 3620 void Simulator::DecodeTypeRegisterSPECIAL3() { |
3846 const int32_t& rt_reg, | 3621 int32_t alu_out; |
3847 const int32_t& rd_reg, | 3622 switch (get_instr()->FunctionFieldRaw()) { |
3848 int32_t& alu_out) { | 3623 case INS: { // Mips32r2 instruction. |
3849 switch (instr->FunctionFieldRaw()) { | 3624 // Interpret rd field as 5-bit msb of insert. |
3850 case INS: | 3625 uint16_t msb = rd_reg(); |
| 3626 // Interpret sa field as 5-bit lsb of insert. |
| 3627 uint16_t lsb = sa(); |
| 3628 uint16_t size = msb - lsb + 1; |
| 3629 uint32_t mask = (1 << size) - 1; |
| 3630 alu_out = (rt_u() & ~(mask << lsb)) | ((rs_u() & mask) << lsb); |
3851 // Ins instr leaves result in Rt, rather than Rd. | 3631 // Ins instr leaves result in Rt, rather than Rd. |
3852 set_register(rt_reg, alu_out); | 3632 SetResult(rt_reg(), alu_out); |
3853 TraceRegWr(alu_out); | 3633 break; |
3854 break; | 3634 } |
3855 case EXT: | 3635 case EXT: { // Mips32r2 instruction. |
3856 set_register(rt_reg, alu_out); | 3636 // Interpret rd field as 5-bit msb of extract. |
3857 TraceRegWr(alu_out); | 3637 uint16_t msb = rd_reg(); |
3858 break; | 3638 // Interpret sa field as 5-bit lsb of extract. |
3859 case BSHFL: | 3639 uint16_t lsb = sa(); |
3860 set_register(rd_reg, alu_out); | 3640 uint16_t size = msb + 1; |
3861 TraceRegWr(alu_out); | 3641 uint32_t mask = (1 << size) - 1; |
3862 break; | 3642 alu_out = (rs_u() & (mask << lsb)) >> lsb; |
| 3643 SetResult(rt_reg(), alu_out); |
| 3644 break; |
| 3645 } |
| 3646 case BSHFL: { |
| 3647 int sa = get_instr()->SaFieldRaw() >> kSaShift; |
| 3648 switch (sa) { |
| 3649 case BITSWAP: { |
| 3650 uint32_t input = static_cast<uint32_t>(rt()); |
| 3651 uint32_t output = 0; |
| 3652 uint8_t i_byte, o_byte; |
| 3653 |
| 3654 // Reverse the bit in byte for each individual byte |
| 3655 for (int i = 0; i < 4; i++) { |
| 3656 output = output >> 8; |
| 3657 i_byte = input & 0xff; |
| 3658 |
| 3659 // Fast way to reverse bits in byte |
| 3660 // Devised by Sean Anderson, July 13, 2001 |
| 3661 o_byte = static_cast<uint8_t>(((i_byte * 0x0802LU & 0x22110LU) | |
| 3662 (i_byte * 0x8020LU & 0x88440LU)) * |
| 3663 0x10101LU >> |
| 3664 16); |
| 3665 |
| 3666 output = output | (static_cast<uint32_t>(o_byte << 24)); |
| 3667 input = input >> 8; |
| 3668 } |
| 3669 |
| 3670 alu_out = static_cast<int32_t>(output); |
| 3671 break; |
| 3672 } |
| 3673 case SEB: |
| 3674 case SEH: |
| 3675 case WSBH: |
| 3676 alu_out = 0x12345678; |
| 3677 UNREACHABLE(); |
| 3678 break; |
| 3679 default: { |
| 3680 const uint8_t bp = get_instr()->Bp2Value(); |
| 3681 sa >>= kBp2Bits; |
| 3682 switch (sa) { |
| 3683 case ALIGN: { |
| 3684 if (bp == 0) { |
| 3685 alu_out = static_cast<int32_t>(rt()); |
| 3686 } else { |
| 3687 uint32_t rt_hi = rt() << (8 * bp); |
| 3688 uint32_t rs_lo = rs() >> (8 * (4 - bp)); |
| 3689 alu_out = static_cast<int32_t>(rt_hi | rs_lo); |
| 3690 } |
| 3691 break; |
| 3692 } |
| 3693 default: |
| 3694 alu_out = 0x12345678; |
| 3695 UNREACHABLE(); |
| 3696 break; |
| 3697 } |
| 3698 } |
| 3699 } |
| 3700 SetResult(rd_reg(), alu_out); |
| 3701 break; |
| 3702 } |
3863 default: | 3703 default: |
3864 UNREACHABLE(); | 3704 UNREACHABLE(); |
3865 } | 3705 } |
3866 } | 3706 } |
3867 | 3707 |
3868 | 3708 |
3869 void Simulator::DecodeTypeRegister(Instruction* instr) { | 3709 void Simulator::DecodeTypeRegister(Instruction* instr) { |
3870 // Instruction fields. | |
3871 const Opcode op = instr->OpcodeFieldRaw(); | 3710 const Opcode op = instr->OpcodeFieldRaw(); |
3872 const int32_t rs_reg = instr->RsValue(); | |
3873 const int32_t rs = get_register(rs_reg); | |
3874 const uint32_t rs_u = static_cast<uint32_t>(rs); | |
3875 const int32_t rt_reg = instr->RtValue(); | |
3876 const int32_t rt = get_register(rt_reg); | |
3877 const uint32_t rt_u = static_cast<uint32_t>(rt); | |
3878 const int32_t rd_reg = instr->RdValue(); | |
3879 | |
3880 const int32_t fr_reg = instr->FrValue(); | |
3881 const int32_t fs_reg = instr->FsValue(); | |
3882 const int32_t ft_reg = instr->FtValue(); | |
3883 const int32_t fd_reg = instr->FdValue(); | |
3884 int64_t i64hilo = 0; | |
3885 uint64_t u64hilo = 0; | |
3886 | |
3887 // ALU output. | |
3888 // It should not be used as is. Instructions using it should always | |
3889 // initialize it first. | |
3890 int32_t alu_out = 0x12345678; | |
3891 | |
3892 // For break and trap instructions. | |
3893 bool do_interrupt = false; | |
3894 | |
3895 // For jr and jalr. | |
3896 // Get current pc. | |
3897 int32_t current_pc = get_pc(); | |
3898 // Next pc | |
3899 int32_t next_pc = 0; | |
3900 int32_t return_addr_reg = 31; | |
3901 | 3711 |
3902 // Set up the variables if needed before executing the instruction. | 3712 // Set up the variables if needed before executing the instruction. |
3903 ConfigureTypeRegister(instr, &alu_out, &i64hilo, &u64hilo, &next_pc, | 3713 // ConfigureTypeRegister(instr); |
3904 &return_addr_reg, &do_interrupt); | 3714 set_instr(instr); |
3905 | |
3906 // ---------- Raise exceptions triggered. | |
3907 SignalExceptions(); | |
3908 | 3715 |
3909 // ---------- Execution. | 3716 // ---------- Execution. |
3910 switch (op) { | 3717 switch (op) { |
3911 case COP1: | 3718 case COP1: |
3912 DecodeTypeRegisterCOP1(instr, rs_reg, rs, rs_u, rt_reg, rt, rt_u, rd_reg, | 3719 DecodeTypeRegisterCOP1(); |
3913 fr_reg, fs_reg, ft_reg, fd_reg, i64hilo, u64hilo, | |
3914 alu_out, do_interrupt, current_pc, next_pc, | |
3915 return_addr_reg); | |
3916 break; | 3720 break; |
3917 case COP1X: | 3721 case COP1X: |
3918 DecodeTypeRegisterCOP1X(instr, fr_reg, fs_reg, ft_reg, fd_reg); | 3722 DecodeTypeRegisterCOP1X(); |
3919 break; | 3723 break; |
3920 case SPECIAL: | 3724 case SPECIAL: |
3921 DecodeTypeRegisterSPECIAL(instr, rs_reg, rs, rs_u, rt_reg, rt, rt_u, | 3725 DecodeTypeRegisterSPECIAL(); |
3922 rd_reg, fr_reg, fs_reg, ft_reg, fd_reg, i64hilo, | |
3923 u64hilo, alu_out, do_interrupt, current_pc, | |
3924 next_pc, return_addr_reg); | |
3925 break; | 3726 break; |
3926 case SPECIAL2: | 3727 case SPECIAL2: |
3927 DecodeTypeRegisterSPECIAL2(instr, rd_reg, alu_out); | 3728 DecodeTypeRegisterSPECIAL2(); |
3928 break; | 3729 break; |
3929 case SPECIAL3: | 3730 case SPECIAL3: |
3930 DecodeTypeRegisterSPECIAL3(instr, rt_reg, rd_reg, alu_out); | 3731 DecodeTypeRegisterSPECIAL3(); |
3931 break; | 3732 break; |
3932 // Unimplemented opcodes raised an error in the configuration step before, | |
3933 // so we can use the default here to set the destination register in common | |
3934 // cases. | |
3935 default: | 3733 default: |
3936 set_register(rd_reg, alu_out); | 3734 UNREACHABLE(); |
3937 } | 3735 } |
3938 } | 3736 } |
3939 | 3737 |
3940 | 3738 |
| 3739 // Branch instructions common part. |
| 3740 #define BranchAndLinkHelper(do_branch) \ |
| 3741 execute_branch_delay_instruction = true; \ |
| 3742 if (do_branch) { \ |
| 3743 next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize; \ |
| 3744 set_register(31, current_pc + 2 * Instruction::kInstrSize); \ |
| 3745 } else { \ |
| 3746 next_pc = current_pc + 2 * Instruction::kInstrSize; \ |
| 3747 } |
| 3748 |
| 3749 #define BranchHelper(do_branch) \ |
| 3750 execute_branch_delay_instruction = true; \ |
| 3751 if (do_branch) { \ |
| 3752 next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize; \ |
| 3753 } else { \ |
| 3754 next_pc = current_pc + 2 * Instruction::kInstrSize; \ |
| 3755 } |
| 3756 |
| 3757 |
3941 // Type 2: instructions using a 16 bytes immediate. (e.g. addi, beq). | 3758 // Type 2: instructions using a 16 bytes immediate. (e.g. addi, beq). |
3942 void Simulator::DecodeTypeImmediate(Instruction* instr) { | 3759 void Simulator::DecodeTypeImmediate(Instruction* instr) { |
3943 // Instruction fields. | 3760 // Instruction fields. |
3944 Opcode op = instr->OpcodeFieldRaw(); | 3761 Opcode op = instr->OpcodeFieldRaw(); |
3945 int32_t rs_reg = instr->RsValue(); | 3762 int32_t rs_reg = instr->RsValue(); |
3946 int32_t rs = get_register(instr->RsValue()); | 3763 int32_t rs = get_register(instr->RsValue()); |
3947 uint32_t rs_u = static_cast<uint32_t>(rs); | 3764 uint32_t rs_u = static_cast<uint32_t>(rs); |
3948 int32_t rt_reg = instr->RtValue(); // Destination register. | 3765 int32_t rt_reg = instr->RtValue(); // Destination register. |
3949 int32_t rt = get_register(rt_reg); | 3766 int32_t rt = get_register(rt_reg); |
3950 int16_t imm16 = instr->Imm16Value(); | 3767 int16_t imm16 = instr->Imm16Value(); |
3951 int32_t imm19 = instr->Imm19Value(); | |
3952 int32_t imm21 = instr->Imm21Value(); | 3768 int32_t imm21 = instr->Imm21Value(); |
3953 int32_t imm26 = instr->Imm26Value(); | 3769 int32_t imm26 = instr->Imm26Value(); |
3954 | 3770 |
3955 int32_t ft_reg = instr->FtValue(); // Destination register. | 3771 int32_t ft_reg = instr->FtValue(); // Destination register. |
3956 int64_t ft; | 3772 int64_t ft; |
3957 | 3773 |
3958 // Zero extended immediate. | 3774 // Zero extended immediate. |
3959 uint32_t oe_imm16 = 0xffff & imm16; | 3775 uint32_t oe_imm16 = 0xffff & imm16; |
3960 // Sign extended immediate. | 3776 // Sign extended immediate. |
3961 int32_t se_imm16 = imm16; | 3777 int32_t se_imm16 = imm16; |
3962 int32_t se_imm19 = imm19 | ((imm19 & 0x40000) ? 0xfff80000 : 0); | |
3963 int32_t se_imm26 = imm26 | ((imm26 & 0x2000000) ? 0xfc000000 : 0); | 3778 int32_t se_imm26 = imm26 | ((imm26 & 0x2000000) ? 0xfc000000 : 0); |
3964 | 3779 |
3965 | |
3966 // Get current pc. | 3780 // Get current pc. |
3967 int32_t current_pc = get_pc(); | 3781 int32_t current_pc = get_pc(); |
3968 // Next pc. | 3782 // Next pc. |
3969 int32_t next_pc = bad_ra; | 3783 int32_t next_pc = bad_ra; |
3970 // pc increment | |
3971 int16_t pc_increment; | |
3972 | 3784 |
3973 // Used for conditional branch instructions. | 3785 // Used for conditional branch instructions. |
3974 bool do_branch = false; | |
3975 bool execute_branch_delay_instruction = false; | 3786 bool execute_branch_delay_instruction = false; |
3976 | 3787 |
3977 // Used for arithmetic instructions. | 3788 // Used for arithmetic instructions. |
3978 int32_t alu_out = 0; | 3789 int32_t alu_out = 0; |
3979 // Floating point. | |
3980 double fp_out = 0.0; | |
3981 uint32_t cc, cc_value, fcsr_cc; | |
3982 | 3790 |
3983 // Used for memory instructions. | 3791 // Used for memory instructions. |
3984 int32_t addr = 0x0; | 3792 int32_t addr = 0x0; |
3985 // Value to be written in memory. | |
3986 uint32_t mem_value = 0x0; | |
3987 | 3793 |
3988 // ---------- Configuration (and execution for REGIMM). | 3794 // ---------- Configuration (and execution for REGIMM). |
3989 switch (op) { | 3795 switch (op) { |
3990 // ------------- COP1. Coprocessor instructions. | 3796 // ------------- COP1. Coprocessor instructions. |
3991 case COP1: | 3797 case COP1: |
3992 switch (instr->RsFieldRaw()) { | 3798 switch (instr->RsFieldRaw()) { |
3993 case BC1: // Branch on coprocessor condition. | 3799 case BC1: { // Branch on coprocessor condition. |
3994 cc = instr->FBccValue(); | 3800 // Floating point. |
3995 fcsr_cc = get_fcsr_condition_bit(cc); | 3801 uint32_t cc = instr->FBccValue(); |
3996 cc_value = test_fcsr_bit(fcsr_cc); | 3802 uint32_t fcsr_cc = get_fcsr_condition_bit(cc); |
3997 do_branch = (instr->FBtrueValue()) ? cc_value : !cc_value; | 3803 uint32_t cc_value = test_fcsr_bit(fcsr_cc); |
| 3804 bool do_branch = (instr->FBtrueValue()) ? cc_value : !cc_value; |
3998 execute_branch_delay_instruction = true; | 3805 execute_branch_delay_instruction = true; |
3999 // Set next_pc. | 3806 // Set next_pc. |
4000 if (do_branch) { | 3807 if (do_branch) { |
4001 next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize; | 3808 next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize; |
4002 } else { | 3809 } else { |
4003 next_pc = current_pc + kBranchReturnOffset; | 3810 next_pc = current_pc + kBranchReturnOffset; |
4004 } | 3811 } |
4005 break; | 3812 break; |
| 3813 } |
4006 case BC1EQZ: | 3814 case BC1EQZ: |
4007 ft = get_fpu_register(ft_reg); | 3815 ft = get_fpu_register(ft_reg); |
4008 do_branch = (ft & 0x1) ? false : true; | |
4009 execute_branch_delay_instruction = true; | 3816 execute_branch_delay_instruction = true; |
4010 // Set next_pc. | 3817 // Set next_pc. |
4011 if (do_branch) { | 3818 if (!(ft & 0x1)) { |
4012 next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize; | 3819 next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize; |
4013 } else { | 3820 } else { |
4014 next_pc = current_pc + kBranchReturnOffset; | 3821 next_pc = current_pc + kBranchReturnOffset; |
4015 } | 3822 } |
4016 break; | 3823 break; |
4017 case BC1NEZ: | 3824 case BC1NEZ: |
4018 ft = get_fpu_register(ft_reg); | 3825 ft = get_fpu_register(ft_reg); |
4019 do_branch = (ft & 0x1) ? true : false; | |
4020 execute_branch_delay_instruction = true; | 3826 execute_branch_delay_instruction = true; |
4021 // Set next_pc. | 3827 // Set next_pc. |
4022 if (do_branch) { | 3828 if (ft & 0x1) { |
4023 next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize; | 3829 next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize; |
4024 } else { | 3830 } else { |
4025 next_pc = current_pc + kBranchReturnOffset; | 3831 next_pc = current_pc + kBranchReturnOffset; |
4026 } | 3832 } |
4027 break; | 3833 break; |
4028 default: | 3834 default: |
4029 UNREACHABLE(); | 3835 UNREACHABLE(); |
4030 } | 3836 } |
4031 break; | 3837 break; |
4032 // ------------- REGIMM class. | 3838 // ------------- REGIMM class. |
4033 case REGIMM: | 3839 case REGIMM: |
4034 switch (instr->RtFieldRaw()) { | 3840 switch (instr->RtFieldRaw()) { |
4035 case BLTZ: | 3841 case BLTZ: |
4036 do_branch = (rs < 0); | 3842 BranchHelper(rs < 0); |
| 3843 break; |
| 3844 case BGEZ: |
| 3845 BranchHelper(rs >= 0); |
4037 break; | 3846 break; |
4038 case BLTZAL: | 3847 case BLTZAL: |
4039 do_branch = rs < 0; | 3848 BranchAndLinkHelper(rs < 0); |
4040 break; | |
4041 case BGEZ: | |
4042 do_branch = rs >= 0; | |
4043 break; | 3849 break; |
4044 case BGEZAL: | 3850 case BGEZAL: |
4045 do_branch = rs >= 0; | 3851 BranchAndLinkHelper(rs >= 0); |
4046 break; | 3852 break; |
4047 default: | 3853 default: |
4048 UNREACHABLE(); | 3854 UNREACHABLE(); |
4049 } | 3855 } |
4050 switch (instr->RtFieldRaw()) { | 3856 break; // case REGIMM. |
4051 case BLTZ: | |
4052 case BLTZAL: | |
4053 case BGEZ: | |
4054 case BGEZAL: | |
4055 // Branch instructions common part. | |
4056 execute_branch_delay_instruction = true; | |
4057 // Set next_pc. | |
4058 if (do_branch) { | |
4059 next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize; | |
4060 if (instr->IsLinkingInstruction()) { | |
4061 set_register(31, current_pc + kBranchReturnOffset); | |
4062 } | |
4063 } else { | |
4064 next_pc = current_pc + kBranchReturnOffset; | |
4065 } | |
4066 default: | |
4067 break; | |
4068 } | |
4069 break; // case REGIMM. | |
4070 // ------------- Branch instructions. | 3857 // ------------- Branch instructions. |
4071 // When comparing to zero, the encoding of rt field is always 0, so we don't | 3858 // When comparing to zero, the encoding of rt field is always 0, so we don't |
4072 // need to replace rt with zero. | 3859 // need to replace rt with zero. |
4073 case BEQ: | 3860 case BEQ: |
4074 do_branch = (rs == rt); | 3861 BranchHelper(rs == rt); |
4075 break; | 3862 break; |
4076 case BNE: | 3863 case BNE: |
4077 do_branch = rs != rt; | 3864 BranchHelper(rs != rt); |
4078 break; | 3865 break; |
4079 case BLEZ: | 3866 case BLEZ: |
4080 do_branch = rs <= 0; | 3867 BranchHelper(rs <= 0); |
4081 break; | 3868 break; |
4082 case BGTZ: | 3869 case BGTZ: |
4083 do_branch = rs > 0; | 3870 BranchHelper(rs > 0); |
4084 break; | 3871 break; |
4085 case POP66: { | 3872 case POP66: { |
4086 if (rs_reg) { // BEQZC | 3873 if (rs_reg) { // BEQZC |
4087 int32_t se_imm21 = | 3874 int32_t se_imm21 = |
4088 static_cast<int32_t>(imm21 << (kOpcodeBits + kRsBits)); | 3875 static_cast<int32_t>(imm21 << (kOpcodeBits + kRsBits)); |
4089 se_imm21 = se_imm21 >> (kOpcodeBits + kRsBits); | 3876 se_imm21 = se_imm21 >> (kOpcodeBits + kRsBits); |
4090 if (rs == 0) | 3877 if (rs == 0) |
4091 next_pc = current_pc + 4 + (se_imm21 << 2); | 3878 next_pc = current_pc + 4 + (se_imm21 << 2); |
4092 else | 3879 else |
4093 next_pc = current_pc + 4; | 3880 next_pc = current_pc + 4; |
(...skipping 12 matching lines...) Expand all Loading... |
4106 set_register(31, current_pc + 4); | 3893 set_register(31, current_pc + 4); |
4107 next_pc = current_pc + 4 + (se_imm26 << 2); | 3894 next_pc = current_pc + 4 + (se_imm26 << 2); |
4108 set_pc(next_pc); | 3895 set_pc(next_pc); |
4109 pc_modified_ = true; | 3896 pc_modified_ = true; |
4110 break; | 3897 break; |
4111 } | 3898 } |
4112 // ------------- Arithmetic instructions. | 3899 // ------------- Arithmetic instructions. |
4113 case ADDI: | 3900 case ADDI: |
4114 if (HaveSameSign(rs, se_imm16)) { | 3901 if (HaveSameSign(rs, se_imm16)) { |
4115 if (rs > 0) { | 3902 if (rs > 0) { |
4116 exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue - se_imm16); | 3903 if (rs <= (Registers::kMaxValue - se_imm16)) { |
| 3904 SignalException(kIntegerOverflow); |
| 3905 } |
4117 } else if (rs < 0) { | 3906 } else if (rs < 0) { |
4118 exceptions[kIntegerUnderflow] = | 3907 if (rs >= (Registers::kMinValue - se_imm16)) { |
4119 rs < (Registers::kMinValue - se_imm16); | 3908 SignalException(kIntegerUnderflow); |
| 3909 } |
4120 } | 3910 } |
4121 } | 3911 } |
4122 alu_out = rs + se_imm16; | 3912 SetResult(rt_reg, rs + se_imm16); |
4123 break; | 3913 break; |
4124 case ADDIU: | 3914 case ADDIU: |
4125 alu_out = rs + se_imm16; | 3915 SetResult(rt_reg, rs + se_imm16); |
4126 break; | 3916 break; |
4127 case SLTI: | 3917 case SLTI: |
4128 alu_out = (rs < se_imm16) ? 1 : 0; | 3918 SetResult(rt_reg, rs < se_imm16 ? 1 : 0); |
4129 break; | 3919 break; |
4130 case SLTIU: | 3920 case SLTIU: |
4131 alu_out = (rs_u < static_cast<uint32_t>(se_imm16)) ? 1 : 0; | 3921 SetResult(rt_reg, rs_u < static_cast<uint32_t>(se_imm16) ? 1 : 0); |
4132 break; | 3922 break; |
4133 case ANDI: | 3923 case ANDI: |
4134 alu_out = rs & oe_imm16; | 3924 SetResult(rt_reg, rs & oe_imm16); |
4135 break; | 3925 break; |
4136 case ORI: | 3926 case ORI: |
4137 alu_out = rs | oe_imm16; | 3927 SetResult(rt_reg, rs | oe_imm16); |
4138 break; | 3928 break; |
4139 case XORI: | 3929 case XORI: |
4140 alu_out = rs ^ oe_imm16; | 3930 SetResult(rt_reg, rs ^ oe_imm16); |
4141 break; | 3931 break; |
4142 case LUI: | 3932 case LUI: |
4143 alu_out = (oe_imm16 << 16); | 3933 SetResult(rt_reg, oe_imm16 << 16); |
4144 break; | 3934 break; |
4145 // ------------- Memory instructions. | 3935 // ------------- Memory instructions. |
4146 case LB: | 3936 case LB: |
4147 addr = rs + se_imm16; | 3937 set_register(rt_reg, ReadB(rs + se_imm16)); |
4148 alu_out = ReadB(addr); | |
4149 break; | 3938 break; |
4150 case LH: | 3939 case LH: |
4151 addr = rs + se_imm16; | 3940 set_register(rt_reg, ReadH(rs + se_imm16, instr)); |
4152 alu_out = ReadH(addr, instr); | |
4153 break; | 3941 break; |
4154 case LWL: { | 3942 case LWL: { |
4155 // al_offset is offset of the effective address within an aligned word. | 3943 // al_offset is offset of the effective address within an aligned word. |
4156 uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask; | 3944 uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask; |
4157 uint8_t byte_shift = kPointerAlignmentMask - al_offset; | 3945 uint8_t byte_shift = kPointerAlignmentMask - al_offset; |
4158 uint32_t mask = (1 << byte_shift * 8) - 1; | 3946 uint32_t mask = (1 << byte_shift * 8) - 1; |
4159 addr = rs + se_imm16 - al_offset; | 3947 addr = rs + se_imm16 - al_offset; |
4160 alu_out = ReadW(addr, instr); | 3948 alu_out = ReadW(addr, instr); |
4161 alu_out <<= byte_shift * 8; | 3949 alu_out <<= byte_shift * 8; |
4162 alu_out |= rt & mask; | 3950 alu_out |= rt & mask; |
| 3951 set_register(rt_reg, alu_out); |
4163 break; | 3952 break; |
4164 } | 3953 } |
4165 case LW: | 3954 case LW: |
4166 addr = rs + se_imm16; | 3955 set_register(rt_reg, ReadW(rs + se_imm16, instr)); |
4167 alu_out = ReadW(addr, instr); | |
4168 break; | 3956 break; |
4169 case LBU: | 3957 case LBU: |
4170 addr = rs + se_imm16; | 3958 set_register(rt_reg, ReadBU(rs + se_imm16)); |
4171 alu_out = ReadBU(addr); | |
4172 break; | 3959 break; |
4173 case LHU: | 3960 case LHU: |
4174 addr = rs + se_imm16; | 3961 set_register(rt_reg, ReadHU(rs + se_imm16, instr)); |
4175 alu_out = ReadHU(addr, instr); | |
4176 break; | 3962 break; |
4177 case LWR: { | 3963 case LWR: { |
4178 // al_offset is offset of the effective address within an aligned word. | 3964 // al_offset is offset of the effective address within an aligned word. |
4179 uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask; | 3965 uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask; |
4180 uint8_t byte_shift = kPointerAlignmentMask - al_offset; | 3966 uint8_t byte_shift = kPointerAlignmentMask - al_offset; |
4181 uint32_t mask = al_offset ? (~0 << (byte_shift + 1) * 8) : 0; | 3967 uint32_t mask = al_offset ? (~0 << (byte_shift + 1) * 8) : 0; |
4182 addr = rs + se_imm16 - al_offset; | 3968 addr = rs + se_imm16 - al_offset; |
4183 alu_out = ReadW(addr, instr); | 3969 alu_out = ReadW(addr, instr); |
4184 alu_out = static_cast<uint32_t> (alu_out) >> al_offset * 8; | 3970 alu_out = static_cast<uint32_t> (alu_out) >> al_offset * 8; |
4185 alu_out |= rt & mask; | 3971 alu_out |= rt & mask; |
| 3972 set_register(rt_reg, alu_out); |
4186 break; | 3973 break; |
4187 } | 3974 } |
4188 case SB: | 3975 case SB: |
4189 addr = rs + se_imm16; | 3976 WriteB(rs + se_imm16, static_cast<int8_t>(rt)); |
4190 break; | 3977 break; |
4191 case SH: | 3978 case SH: |
4192 addr = rs + se_imm16; | 3979 WriteH(rs + se_imm16, static_cast<uint16_t>(rt), instr); |
4193 break; | 3980 break; |
4194 case SWL: { | 3981 case SWL: { |
4195 uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask; | 3982 uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask; |
4196 uint8_t byte_shift = kPointerAlignmentMask - al_offset; | 3983 uint8_t byte_shift = kPointerAlignmentMask - al_offset; |
4197 uint32_t mask = byte_shift ? (~0 << (al_offset + 1) * 8) : 0; | 3984 uint32_t mask = byte_shift ? (~0 << (al_offset + 1) * 8) : 0; |
4198 addr = rs + se_imm16 - al_offset; | 3985 addr = rs + se_imm16 - al_offset; |
4199 mem_value = ReadW(addr, instr) & mask; | 3986 // Value to be written in memory. |
| 3987 uint32_t mem_value = ReadW(addr, instr) & mask; |
4200 mem_value |= static_cast<uint32_t>(rt) >> byte_shift * 8; | 3988 mem_value |= static_cast<uint32_t>(rt) >> byte_shift * 8; |
| 3989 WriteW(addr, mem_value, instr); |
4201 break; | 3990 break; |
4202 } | 3991 } |
4203 case SW: | 3992 case SW: |
4204 addr = rs + se_imm16; | 3993 WriteW(rs + se_imm16, rt, instr); |
4205 break; | 3994 break; |
4206 case SWR: { | 3995 case SWR: { |
4207 uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask; | 3996 uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask; |
4208 uint32_t mask = (1 << al_offset * 8) - 1; | 3997 uint32_t mask = (1 << al_offset * 8) - 1; |
4209 addr = rs + se_imm16 - al_offset; | 3998 addr = rs + se_imm16 - al_offset; |
4210 mem_value = ReadW(addr, instr); | 3999 uint32_t mem_value = ReadW(addr, instr); |
4211 mem_value = (rt << al_offset * 8) | (mem_value & mask); | 4000 mem_value = (rt << al_offset * 8) | (mem_value & mask); |
| 4001 WriteW(addr, mem_value, instr); |
4212 break; | 4002 break; |
4213 } | 4003 } |
4214 case LWC1: | 4004 case LWC1: |
4215 addr = rs + se_imm16; | 4005 set_fpu_register_hi_word(ft_reg, 0); |
4216 alu_out = ReadW(addr, instr); | 4006 set_fpu_register_word(ft_reg, ReadW(rs + se_imm16, instr)); |
4217 break; | 4007 break; |
4218 case LDC1: | 4008 case LDC1: |
4219 addr = rs + se_imm16; | 4009 set_fpu_register_double(ft_reg, ReadD(rs + se_imm16, instr)); |
4220 fp_out = ReadD(addr, instr); | |
4221 break; | 4010 break; |
4222 case SWC1: | 4011 case SWC1: |
| 4012 WriteW(rs + se_imm16, get_fpu_register_word(ft_reg), instr); |
| 4013 break; |
4223 case SDC1: | 4014 case SDC1: |
4224 addr = rs + se_imm16; | 4015 WriteD(rs + se_imm16, get_fpu_register_double(ft_reg), instr); |
4225 break; | 4016 break; |
4226 // ------------- JIALC and BNEZC instructions. | 4017 // ------------- JIALC and BNEZC instructions. |
4227 case POP76: | 4018 case POP76: { |
4228 // Next pc. | 4019 // Next pc. |
4229 next_pc = rt + se_imm16; | 4020 next_pc = rt + se_imm16; |
4230 // The instruction after the jump is NOT executed. | 4021 // The instruction after the jump is NOT executed. |
4231 pc_increment = Instruction::kInstrSize; | 4022 int16_t pc_increment = Instruction::kInstrSize; |
4232 if (instr->IsLinkingInstruction()) { | 4023 if (instr->IsLinkingInstruction()) { |
4233 set_register(31, current_pc + pc_increment); | 4024 set_register(31, current_pc + pc_increment); |
4234 } | 4025 } |
4235 set_pc(next_pc); | 4026 set_pc(next_pc); |
4236 pc_modified_ = true; | 4027 pc_modified_ = true; |
4237 break; | 4028 break; |
| 4029 } |
4238 // ------------- PC-Relative instructions. | 4030 // ------------- PC-Relative instructions. |
4239 case PCREL: { | 4031 case PCREL: { |
4240 // rt field: checking 5-bits. | 4032 // rt field: checking 5-bits. |
4241 uint8_t rt = (imm21 >> kImm16Bits); | 4033 uint8_t rt = (imm21 >> kImm16Bits); |
4242 switch (rt) { | 4034 switch (rt) { |
4243 case ALUIPC: | 4035 case ALUIPC: |
4244 addr = current_pc + (se_imm16 << 16); | 4036 addr = current_pc + (se_imm16 << 16); |
4245 alu_out = static_cast<int64_t>(~0x0FFFF) & addr; | 4037 alu_out = static_cast<int64_t>(~0x0FFFF) & addr; |
4246 break; | 4038 break; |
4247 case AUIPC: | 4039 case AUIPC: |
4248 alu_out = current_pc + (se_imm16 << 16); | 4040 alu_out = current_pc + (se_imm16 << 16); |
4249 break; | 4041 break; |
4250 default: { | 4042 default: { |
| 4043 int32_t imm19 = instr->Imm19Value(); |
4251 // rt field: checking the most significant 2-bits. | 4044 // rt field: checking the most significant 2-bits. |
4252 rt = (imm21 >> kImm19Bits); | 4045 rt = (imm21 >> kImm19Bits); |
4253 switch (rt) { | 4046 switch (rt) { |
4254 case LWPC: { | 4047 case LWPC: { |
4255 int32_t offset = imm19; | |
4256 // Set sign. | 4048 // Set sign. |
4257 offset <<= (kOpcodeBits + kRsBits + 2); | 4049 imm19 <<= (kOpcodeBits + kRsBits + 2); |
4258 offset >>= (kOpcodeBits + kRsBits + 2); | 4050 imm19 >>= (kOpcodeBits + kRsBits + 2); |
4259 addr = current_pc + (offset << 2); | 4051 addr = current_pc + (imm19 << 2); |
4260 uint32_t* ptr = reinterpret_cast<uint32_t*>(addr); | 4052 uint32_t* ptr = reinterpret_cast<uint32_t*>(addr); |
4261 alu_out = *ptr; | 4053 alu_out = *ptr; |
4262 break; | 4054 break; |
4263 } | 4055 } |
4264 case ADDIUPC: | 4056 case ADDIUPC: { |
| 4057 int32_t se_imm19 = imm19 | ((imm19 & 0x40000) ? 0xfff80000 : 0); |
4265 alu_out = current_pc + (se_imm19 << 2); | 4058 alu_out = current_pc + (se_imm19 << 2); |
4266 break; | 4059 break; |
| 4060 } |
4267 default: | 4061 default: |
4268 UNREACHABLE(); | 4062 UNREACHABLE(); |
4269 break; | 4063 break; |
4270 } | 4064 } |
4271 } | 4065 } |
4272 } | 4066 } |
| 4067 set_register(rs_reg, alu_out); |
4273 break; | 4068 break; |
4274 } | 4069 } |
4275 default: | 4070 default: |
4276 UNREACHABLE(); | 4071 UNREACHABLE(); |
4277 } | 4072 } |
4278 | 4073 |
4279 // ---------- Raise exceptions triggered. | |
4280 SignalExceptions(); | |
4281 | |
4282 // ---------- Execution. | |
4283 switch (op) { | |
4284 // ------------- Branch instructions. | |
4285 case BEQ: | |
4286 case BNE: | |
4287 case BLEZ: | |
4288 case BGTZ: | |
4289 // Branch instructions common part. | |
4290 execute_branch_delay_instruction = true; | |
4291 // Set next_pc. | |
4292 if (do_branch) { | |
4293 next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize; | |
4294 if (instr->IsLinkingInstruction()) { | |
4295 set_register(31, current_pc + 2* Instruction::kInstrSize); | |
4296 } | |
4297 } else { | |
4298 next_pc = current_pc + 2 * Instruction::kInstrSize; | |
4299 } | |
4300 break; | |
4301 // ------------- Arithmetic instructions. | |
4302 case ADDI: | |
4303 case ADDIU: | |
4304 case SLTI: | |
4305 case SLTIU: | |
4306 case ANDI: | |
4307 case ORI: | |
4308 case XORI: | |
4309 case LUI: | |
4310 set_register(rt_reg, alu_out); | |
4311 TraceRegWr(alu_out); | |
4312 break; | |
4313 // ------------- Memory instructions. | |
4314 case LB: | |
4315 case LH: | |
4316 case LWL: | |
4317 case LW: | |
4318 case LBU: | |
4319 case LHU: | |
4320 case LWR: | |
4321 set_register(rt_reg, alu_out); | |
4322 break; | |
4323 case SB: | |
4324 WriteB(addr, static_cast<int8_t>(rt)); | |
4325 break; | |
4326 case SH: | |
4327 WriteH(addr, static_cast<uint16_t>(rt), instr); | |
4328 break; | |
4329 case SWL: | |
4330 WriteW(addr, mem_value, instr); | |
4331 break; | |
4332 case SW: | |
4333 WriteW(addr, rt, instr); | |
4334 break; | |
4335 case SWR: | |
4336 WriteW(addr, mem_value, instr); | |
4337 break; | |
4338 case LWC1: | |
4339 set_fpu_register_hi_word(ft_reg, 0); | |
4340 set_fpu_register_word(ft_reg, alu_out); | |
4341 break; | |
4342 case LDC1: | |
4343 set_fpu_register_double(ft_reg, fp_out); | |
4344 break; | |
4345 case SWC1: | |
4346 addr = rs + se_imm16; | |
4347 WriteW(addr, get_fpu_register_word(ft_reg), instr); | |
4348 break; | |
4349 case SDC1: | |
4350 addr = rs + se_imm16; | |
4351 WriteD(addr, get_fpu_register_double(ft_reg), instr); | |
4352 break; | |
4353 case PCREL: | |
4354 set_register(rs_reg, alu_out); | |
4355 default: | |
4356 break; | |
4357 } | |
4358 | |
4359 | |
4360 if (execute_branch_delay_instruction) { | 4074 if (execute_branch_delay_instruction) { |
4361 // Execute branch delay slot | 4075 // Execute branch delay slot |
4362 // We don't check for end_sim_pc. First it should not be met as the current | 4076 // We don't check for end_sim_pc. First it should not be met as the current |
4363 // pc is valid. Secondly a jump should always execute its branch delay slot. | 4077 // pc is valid. Secondly a jump should always execute its branch delay slot. |
4364 Instruction* branch_delay_instr = | 4078 Instruction* branch_delay_instr = |
4365 reinterpret_cast<Instruction*>(current_pc+Instruction::kInstrSize); | 4079 reinterpret_cast<Instruction*>(current_pc+Instruction::kInstrSize); |
4366 BranchDelayInstructionDecode(branch_delay_instr); | 4080 BranchDelayInstructionDecode(branch_delay_instr); |
4367 } | 4081 } |
4368 | 4082 |
4369 // If needed update pc after the branch delay execution. | 4083 // If needed update pc after the branch delay execution. |
4370 if (next_pc != bad_ra) { | 4084 if (next_pc != bad_ra) { |
4371 set_pc(next_pc); | 4085 set_pc(next_pc); |
4372 } | 4086 } |
4373 } | 4087 } |
4374 | 4088 |
| 4089 #undef BranchHelper |
| 4090 #undef BranchAndLinkHelper |
| 4091 |
4375 | 4092 |
4376 // Type 3: instructions using a 26 bytes immediate. (e.g. j, jal). | 4093 // Type 3: instructions using a 26 bytes immediate. (e.g. j, jal). |
4377 void Simulator::DecodeTypeJump(Instruction* instr) { | 4094 void Simulator::DecodeTypeJump(Instruction* instr) { |
4378 // Get current pc. | 4095 // Get current pc. |
4379 int32_t current_pc = get_pc(); | 4096 int32_t current_pc = get_pc(); |
4380 // Get unchanged bits of pc. | 4097 // Get unchanged bits of pc. |
4381 int32_t pc_high_bits = current_pc & 0xf0000000; | 4098 int32_t pc_high_bits = current_pc & 0xf0000000; |
4382 // Next pc. | 4099 // Next pc. |
4383 int32_t next_pc = pc_high_bits | (instr->Imm26Value() << 2); | 4100 int32_t next_pc = pc_high_bits | (instr->Imm26Value() << 2); |
4384 | 4101 |
(...skipping 21 matching lines...) Expand all Loading... |
4406 } | 4123 } |
4407 pc_modified_ = false; | 4124 pc_modified_ = false; |
4408 v8::internal::EmbeddedVector<char, 256> buffer; | 4125 v8::internal::EmbeddedVector<char, 256> buffer; |
4409 if (::v8::internal::FLAG_trace_sim) { | 4126 if (::v8::internal::FLAG_trace_sim) { |
4410 SNPrintF(trace_buf_, "%s", ""); | 4127 SNPrintF(trace_buf_, "%s", ""); |
4411 disasm::NameConverter converter; | 4128 disasm::NameConverter converter; |
4412 disasm::Disassembler dasm(converter); | 4129 disasm::Disassembler dasm(converter); |
4413 dasm.InstructionDecode(buffer, reinterpret_cast<byte*>(instr)); | 4130 dasm.InstructionDecode(buffer, reinterpret_cast<byte*>(instr)); |
4414 } | 4131 } |
4415 | 4132 |
4416 switch (instr->InstructionType()) { | 4133 switch (instr->InstructionType(Instruction::TypeChecks::EXTRA)) { |
4417 case Instruction::kRegisterType: | 4134 case Instruction::kRegisterType: |
4418 DecodeTypeRegister(instr); | 4135 DecodeTypeRegister(instr); |
4419 break; | 4136 break; |
4420 case Instruction::kImmediateType: | 4137 case Instruction::kImmediateType: |
4421 DecodeTypeImmediate(instr); | 4138 DecodeTypeImmediate(instr); |
4422 break; | 4139 break; |
4423 case Instruction::kJumpType: | 4140 case Instruction::kJumpType: |
4424 DecodeTypeJump(instr); | 4141 DecodeTypeJump(instr); |
4425 break; | 4142 break; |
4426 default: | 4143 default: |
(...skipping 191 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
4618 | 4335 |
4619 | 4336 |
4620 #undef UNSUPPORTED | 4337 #undef UNSUPPORTED |
4621 | 4338 |
4622 } // namespace internal | 4339 } // namespace internal |
4623 } // namespace v8 | 4340 } // namespace v8 |
4624 | 4341 |
4625 #endif // USE_SIMULATOR | 4342 #endif // USE_SIMULATOR |
4626 | 4343 |
4627 #endif // V8_TARGET_ARCH_MIPS | 4344 #endif // V8_TARGET_ARCH_MIPS |
OLD | NEW |