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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #if V8_TARGET_ARCH_MIPS | 5 #if V8_TARGET_ARCH_MIPS |
6 | 6 |
7 #include "src/mips/constants-mips.h" | 7 #include "src/mips/constants-mips.h" |
8 | 8 |
9 namespace v8 { | 9 namespace v8 { |
10 namespace internal { | 10 namespace internal { |
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212 case TEQ: | 212 case TEQ: |
213 case TNE: | 213 case TNE: |
214 return true; | 214 return true; |
215 default: | 215 default: |
216 return false; | 216 return false; |
217 } | 217 } |
218 } | 218 } |
219 } | 219 } |
220 | 220 |
221 | 221 |
222 Instruction::Type Instruction::InstructionType() const { | |
223 switch (OpcodeFieldRaw()) { | |
224 case SPECIAL: | |
225 switch (FunctionFieldRaw()) { | |
226 case JR: | |
227 case JALR: | |
228 case BREAK: | |
229 case SLL: | |
230 case SRL: | |
231 case SRA: | |
232 case SLLV: | |
233 case SRLV: | |
234 case SRAV: | |
235 case MFHI: | |
236 case MFLO: | |
237 case MULT: | |
238 case MULTU: | |
239 case DIV: | |
240 case DIVU: | |
241 case ADD: | |
242 case ADDU: | |
243 case SUB: | |
244 case SUBU: | |
245 case AND: | |
246 case OR: | |
247 case XOR: | |
248 case NOR: | |
249 case SLT: | |
250 case SLTU: | |
251 case TGE: | |
252 case TGEU: | |
253 case TLT: | |
254 case TLTU: | |
255 case TEQ: | |
256 case TNE: | |
257 case MOVZ: | |
258 case MOVN: | |
259 case MOVCI: | |
260 case SELEQZ_S: | |
261 case SELNEZ_S: | |
262 return kRegisterType; | |
263 default: | |
264 return kUnsupported; | |
265 } | |
266 break; | |
267 case SPECIAL2: | |
268 switch (FunctionFieldRaw()) { | |
269 case MUL: | |
270 case CLZ: | |
271 return kRegisterType; | |
272 default: | |
273 return kUnsupported; | |
274 } | |
275 break; | |
276 case SPECIAL3: | |
277 switch (FunctionFieldRaw()) { | |
278 case INS: | |
279 case EXT: | |
280 return kRegisterType; | |
281 case BSHFL: { | |
282 int sa = SaFieldRaw() >> kSaShift; | |
283 switch (sa) { | |
284 case BITSWAP: | |
285 return kRegisterType; | |
286 case WSBH: | |
287 case SEB: | |
288 case SEH: | |
289 return kUnsupported; | |
290 } | |
291 sa >>= kBp2Bits; | |
292 switch (sa) { | |
293 case ALIGN: | |
294 return kRegisterType; | |
295 default: | |
296 return kUnsupported; | |
297 } | |
298 } | |
299 default: | |
300 return kUnsupported; | |
301 } | |
302 break; | |
303 case COP1: // Coprocessor instructions. | |
304 switch (RsFieldRawNoAssert()) { | |
305 case BC1: // Branch on coprocessor condition. | |
306 case BC1EQZ: | |
307 case BC1NEZ: | |
308 return kImmediateType; | |
309 default: | |
310 return kRegisterType; | |
311 } | |
312 break; | |
313 case COP1X: | |
314 return kRegisterType; | |
315 // 16 bits Immediate type instructions. e.g.: addi dest, src, imm16. | |
316 case REGIMM: | |
317 case BEQ: | |
318 case BNE: | |
319 case BLEZ: | |
320 case BGTZ: | |
321 case ADDI: | |
322 case DADDI: | |
323 case ADDIU: | |
324 case SLTI: | |
325 case SLTIU: | |
326 case ANDI: | |
327 case ORI: | |
328 case XORI: | |
329 case LUI: | |
330 case BEQL: | |
331 case BNEL: | |
332 case BLEZL: | |
333 case BGTZL: | |
334 case POP66: | |
335 case POP76: | |
336 case LB: | |
337 case LH: | |
338 case LWL: | |
339 case LW: | |
340 case LBU: | |
341 case LHU: | |
342 case LWR: | |
343 case SB: | |
344 case SH: | |
345 case SWL: | |
346 case SW: | |
347 case SWR: | |
348 case LWC1: | |
349 case LDC1: | |
350 case SWC1: | |
351 case SDC1: | |
352 case PCREL: | |
353 case BC: | |
354 case BALC: | |
355 return kImmediateType; | |
356 // 26 bits immediate type instructions. e.g.: j imm26. | |
357 case J: | |
358 case JAL: | |
359 return kJumpType; | |
360 default: | |
361 return kUnsupported; | |
362 } | |
363 return kUnsupported; | |
364 } | |
365 | |
366 | |
367 } // namespace internal | 222 } // namespace internal |
368 } // namespace v8 | 223 } // namespace v8 |
369 | 224 |
370 #endif // V8_TARGET_ARCH_MIPS | 225 #endif // V8_TARGET_ARCH_MIPS |
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