Subzero. Changes the declaration for ARM32 registers.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 164 matching lines @@
   // Instead, initialize in some sort of static initializer for the
   // class.
   // Limit this size (or do all bitsets need to be the same width)???
   llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM);
   ScratchRegs.resize(RegARM32::Reg_NUM);
 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
-          isFP32, isFP64, isVec128)                                            \
+          isFP32, isFP64, isVec128, alias_init)                                \
   IntegerRegisters[RegARM32::val] = isInt;                                     \
   Float32Registers[RegARM32::val] = isFP32;                                    \
   Float64Registers[RegARM32::val] = isFP64;                                    \
   VectorRegisters[RegARM32::val] = isVec128;                                   \
   RegisterAliases[RegARM32::val].resize(RegARM32::Reg_NUM);                    \
-  RegisterAliases[RegARM32::val].set(RegARM32::val);                           \
+  for (SizeT RegAlias : alias_init) {                                          \
+    assert(!RegisterAliases[RegARM32::val][RegAlias] &&                        \
+           "Duplicate alias for " #val);                                       \
+    RegisterAliases[RegARM32::val].set(RegAlias);                              \
+  }                                                                            \
+  RegisterAliases[RegARM32::val].resize(RegARM32::Reg_NUM);                    \
+  assert(RegisterAliases[RegARM32::val][RegARM32::val]);                       \
   ScratchRegs[RegARM32::val] = scratch;
   REGARM32_TABLE;
 #undef X
   TypeToRegisterSet[IceType_void] = InvalidRegisters;
   TypeToRegisterSet[IceType_i1] = IntegerRegisters;
   TypeToRegisterSet[IceType_i8] = IntegerRegisters;
   TypeToRegisterSet[IceType_i16] = IntegerRegisters;
   TypeToRegisterSet[IceType_i32] = IntegerRegisters;
   TypeToRegisterSet[IceType_i64] = IntegerRegisters;
   TypeToRegisterSet[IceType_f32] = Float32Registers;
@@ skipping 159 matching lines @@
     return Br->optimizeBranch(NextNode);
   }
   return false;
 }
 
 IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const {
   assert(RegNum < RegARM32::Reg_NUM);
   (void)Ty;
   static const char *RegNames[] = {
 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
-          isFP32, isFP64, isVec128)                                            \
+          isFP32, isFP64, isVec128, alias_init)                                \
   name,
       REGARM32_TABLE
 #undef X
   };
 
   return RegNames[RegNum];
 }
 
 Variable *TargetARM32::getPhysicalRegister(SizeT RegNum, Type Ty) {
   if (Ty == IceType_void)
@@ skipping 78 matching lines @@
   *Reg = RegARM32::Reg_r0 + NumGPRRegsUsed;
   ++NumGPRRegsUsed;
   return true;
 }
 
 bool TargetARM32::CallingConv::FPInReg(Type Ty, int32_t *Reg) {
   if (NumFPRegUnits >= ARM32_MAX_FP_REG_UNITS)
     return false;
   if (isVectorType(Ty)) {
     NumFPRegUnits = Utils::applyAlignment(NumFPRegUnits, 4);
-    *Reg = RegARM32::Reg_q0 + (NumFPRegUnits / 4);
+    // Q registers are declared in reverse order, so
+    // RegARM32::Reg_q0 > RegARM32::Reg_q1. Therefore, we need to subtract
+    // NumFPRegUnits from Reg_q0. Same thing goes for D registers.
+    static_assert(RegARM32::Reg_q0 > RegARM32::Reg_q1,
+                  "ARM32 Q registers are possibly declared incorrectly.");
+    *Reg = RegARM32::Reg_q0 - (NumFPRegUnits / 4);
     NumFPRegUnits += 4;
     // If this bumps us past the boundary, don't allocate to a register
     // and leave any previously speculatively consumed registers as consumed.
     if (NumFPRegUnits > ARM32_MAX_FP_REG_UNITS)
       return false;
   } else if (Ty == IceType_f64) {
+    static_assert(RegARM32::Reg_d0 > RegARM32::Reg_d1,
+                  "ARM32 D registers are possibly declared incorrectly.");
     NumFPRegUnits = Utils::applyAlignment(NumFPRegUnits, 2);
-    *Reg = RegARM32::Reg_d0 + (NumFPRegUnits / 2);
+    *Reg = RegARM32::Reg_d0 - (NumFPRegUnits / 2);
     NumFPRegUnits += 2;
     // If this bumps us past the boundary, don't allocate to a register
     // and leave any previously speculatively consumed registers as consumed.
     if (NumFPRegUnits > ARM32_MAX_FP_REG_UNITS)
       return false;
   } else {
+    static_assert(RegARM32::Reg_s0 < RegARM32::Reg_s1,
+                  "ARM32 S registers are possibly declared incorrectly.");
     assert(Ty == IceType_f32);
     *Reg = RegARM32::Reg_s0 + NumFPRegUnits;
     ++NumFPRegUnits;
   }
   return true;
 }
 
 void TargetARM32::lowerArguments() {
   VarList &Args = Func->getArgs();
   TargetARM32::CallingConv CC;
@@ skipping 650 matching lines @@
   }
   llvm_unreachable("Unsupported operand type");
   return nullptr;
 }
 
 llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
                                                  RegSetMask Exclude) const {
   llvm::SmallBitVector Registers(RegARM32::Reg_NUM);
 
 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
-          isFP32, isFP64, isVec128)                                            \
+          isFP32, isFP64, isVec128, alias_init)                                \
   if (scratch && (Include & RegSet_CallerSave))                                \
     Registers[RegARM32::val] = true;                                           \
   if (preserved && (Include & RegSet_CalleeSave))                              \
     Registers[RegARM32::val] = true;                                           \
   if (stackptr && (Include & RegSet_StackPointer))                             \
     Registers[RegARM32::val] = true;                                           \
   if (frameptr && (Include & RegSet_FramePointer))                             \
     Registers[RegARM32::val] = true;                                           \
   if (scratch && (Exclude & RegSet_CallerSave))                                \
     Registers[RegARM32::val] = false;                                          \
@@ skipping 1875 matching lines @@
       << ".eabi_attribute 68, 1   @ Tag_Virtualization_use\n";
   if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) {
     Str << ".eabi_attribute 44, 2   @ Tag_DIV_use\n";
   }
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 } // end of namespace Ice