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Issue 1310863007: Subzero. Changes the declaration for ARM32 registers. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Addresses comments. Created 5 years, 3 months ago
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1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===// 1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of ARM32 instructions in the form of x-macros. 10 // This file defines properties of ARM32 instructions in the form of x-macros.
11 // 11 //
12 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===//
13 13
14 #ifndef SUBZERO_SRC_ICEINSTARM32_DEF 14 #ifndef SUBZERO_SRC_ICEINSTARM32_DEF
15 #define SUBZERO_SRC_ICEINSTARM32_DEF 15 #define SUBZERO_SRC_ICEINSTARM32_DEF
16 16
17 // NOTE: PC and SP are not considered isInt, to avoid register allocating. 17 // NOTE: PC and SP are not considered isInt, to avoid register allocating.
18 // 18 //
19 // For the NaCl sandbox we also need to r9 for TLS, so just reserve always. 19 // For the NaCl sandbox we also need to r9 for TLS, so just reserve always.
20 // TODO(jvoung): Allow r9 to be isInt when sandboxing is turned off 20 // TODO(jvoung): Allow r9 to be isInt when sandboxing is turned off
21 // (native mode). 21 // (native mode).
22 // 22 //
23 // IP is not considered isInt to reserve it as a scratch register. A scratch 23 // IP is not considered isInt to reserve it as a scratch register. A scratch
24 // register is useful for expanding instructions post-register allocation. 24 // register is useful for expanding instructions post-register allocation.
25 // 25 //
26 // LR is not considered isInt to avoid being allocated as a register. 26 // LR is not considered isInt to avoid being allocated as a register.
27 // It is technically preserved, but save/restore is handled separately, 27 // It is technically preserved, but save/restore is handled separately,
28 // based on whether or not the function MaybeLeafFunc. 28 // based on whether or not the function MaybeLeafFunc.
29
30 // ALIASESn is a family of macros that we use to define register aliasing in
31 // ARM32. n indicates how many aliases are being provided to the macro. It
32 // assumes the parameters are register names declared in a namespace/class named
33 // RegARM32.
34 #define ALIASES1(r0) \
35 {RegARM32::r0}
36 #define ALIASES2(r0, r1) \
37 {RegARM32::r0, RegARM32::r1}
38 #define ALIASES3(r0, r1, r2) \
39 {RegARM32::r0, RegARM32::r1, RegARM32::r2}
40 #define ALIASES4(r0, r1, r2, r3) \
41 {RegARM32::r0, RegARM32::r1, RegARM32::r2, RegARM32::r3}
42 #define ALIASES7(r0, r1, r2, r3, r4, r5, r6) \
43 {RegARM32::r0, RegARM32::r1, RegARM32::r2, RegARM32::r3, RegARM32::r4, \
44 RegARM32::r5,RegARM32::r6}
45
46
29 #define REGARM32_GPR_TABLE \ 47 #define REGARM32_GPR_TABLE \
30 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 48 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
31 isInt, isFP32, isFP64, isVec128 */ \ 49 isInt, isFP32, isFP64, isVec128, aliases_init */ \
32 X(Reg_r0, 0, "r0", 1, 0, 0, 0, 1, 0, 0, 0) \ 50 X(Reg_r0, 0, "r0", 1, 0, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r0)) \
33 X(Reg_r1, 1, "r1", 1, 0, 0, 0, 1, 0, 0, 0) \ 51 X(Reg_r1, 1, "r1", 1, 0, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r1)) \
34 X(Reg_r2, 2, "r2", 1, 0, 0, 0, 1, 0, 0, 0) \ 52 X(Reg_r2, 2, "r2", 1, 0, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r2)) \
35 X(Reg_r3, 3, "r3", 1, 0, 0, 0, 1, 0, 0, 0) \ 53 X(Reg_r3, 3, "r3", 1, 0, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r3)) \
36 X(Reg_r4, 4, "r4", 0, 1, 0, 0, 1, 0, 0, 0) \ 54 X(Reg_r4, 4, "r4", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r4)) \
37 X(Reg_r5, 5, "r5", 0, 1, 0, 0, 1, 0, 0, 0) \ 55 X(Reg_r5, 5, "r5", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r5)) \
38 X(Reg_r6, 6, "r6", 0, 1, 0, 0, 1, 0, 0, 0) \ 56 X(Reg_r6, 6, "r6", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r6)) \
39 X(Reg_r7, 7, "r7", 0, 1, 0, 0, 1, 0, 0, 0) \ 57 X(Reg_r7, 7, "r7", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r7)) \
40 X(Reg_r8, 8, "r8", 0, 1, 0, 0, 1, 0, 0, 0) \ 58 X(Reg_r8, 8, "r8", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r8)) \
41 X(Reg_r9, 9, "r9", 0, 1, 0, 0, 0, 0, 0, 0) \ 59 X(Reg_r9, 9, "r9", 0, 1, 0, 0, 0, 0, 0, 0, ALIASES1(Reg_r9)) \
42 X(Reg_r10, 10, "r10", 0, 1, 0, 0, 1, 0, 0, 0) \ 60 X(Reg_r10, 10, "r10", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r10)) \
43 X(Reg_fp, 11, "fp", 0, 1, 0, 1, 1, 0, 0, 0) \ 61 X(Reg_fp, 11, "fp", 0, 1, 0, 1, 1, 0, 0, 0, ALIASES1(Reg_fp)) \
44 X(Reg_ip, 12, "ip", 1, 0, 0, 0, 0, 0, 0, 0) \ 62 X(Reg_ip, 12, "ip", 1, 0, 0, 0, 0, 0, 0, 0, ALIASES1(Reg_ip)) \
45 X(Reg_sp, 13, "sp", 0, 0, 1, 0, 0, 0, 0, 0) \ 63 X(Reg_sp, 13, "sp", 0, 0, 1, 0, 0, 0, 0, 0, ALIASES1(Reg_sp)) \
46 X(Reg_lr, 14, "lr", 0, 0, 0, 0, 0, 0, 0, 0) \ 64 X(Reg_lr, 14, "lr", 0, 0, 0, 0, 0, 0, 0, 0, ALIASES1(Reg_lr)) \
47 X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 0, 0, 0) 65 X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 0, 0, 0, ALIASES1(Reg_pc))
48 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 66 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
49 // isInt, isFP32, isFP64, isVec128) 67 // isInt, isFP32, isFP64, isVec128, aliases_init)
50 68
51 // TODO(jvoung): Be able to grab even registers, and the corresponding odd
52 // register for each even register. Want "register units" to encapsulate
53 // the aliasing/overlap.
54 //
55 // S registers 0-15 are scratch, but 16-31 are preserved. 69 // S registers 0-15 are scratch, but 16-31 are preserved.
56 // Regenerate this with the following python script: 70 // Regenerate this with the following python script:
57 // 71 //
58 // def print_sregs(): 72 // def print_sregs():
59 // for i in xrange(0, 32): 73 // for i in xrange(0, 32):
60 // is_scratch = 1 if i < 16 else 0 74 // is_scratch = 1 if i < 16 else 0
61 // is_preserved = 1 if i >= 16 else 0 75 // is_preserved = 1 if i >= 16 else 0
62 // print ('X(Reg_s{regnum:<2}, {regnum:<2}, "s{regnum}", ' + 76 // print (' X(Reg_s{regnum:<2}, {regnum:<2}, "s{regnum}", ' +
63 // '{scratch}, {preserved}, 0, 0, 0, 1, 0, 0) \\').format( 77 // '{scratch}, {preserved}, 0, 0, 0, 1, 0, 0, ' +
64 // regnum=i, scratch=is_scratch, preserved=is_preserved) 78 // 'ALIASES(Reg_s{regnum_s:<2}, Reg_d{regnum:<2}, ' +
79 // 'Reg_q{regnum_q:<2})) \\').format(
80 // regnum=i, regnum_d=i>>1,
81 // regnum_q=i>>2, scratch=is_scratch, preserved=is_preserved)
65 // 82 //
66 // print_sregs() 83 // print_sregs()
67 // 84 //
68 #define REGARM32_FP32_TABLE \ 85 #define REGARM32_FP32_TABLE \
69 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 86 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
70 isInt, isFP32, isFP64, isVec128 */ \ 87 isInt, isFP32, isFP64, isVec128, aliases_init */ \
71 X(Reg_s0, 0, "s0", 1, 0, 0, 0, 0, 1, 0, 0) \ 88 X(Reg_s0 , 0 , "s0" , 1, 0, 0, 0, 0, 1, 0, 0, \
72 X(Reg_s1, 1, "s1", 1, 0, 0, 0, 0, 1, 0, 0) \ 89 ALIASES3(Reg_s0 , Reg_d0 , Reg_q0)) \
73 X(Reg_s2, 2, "s2", 1, 0, 0, 0, 0, 1, 0, 0) \ 90 X(Reg_s1 , 1 , "s1" , 1, 0, 0, 0, 0, 1, 0, 0, \
74 X(Reg_s3, 3, "s3", 1, 0, 0, 0, 0, 1, 0, 0) \ 91 ALIASES3(Reg_s1 , Reg_d0 , Reg_q0)) \
75 X(Reg_s4, 4, "s4", 1, 0, 0, 0, 0, 1, 0, 0) \ 92 X(Reg_s2 , 2 , "s2" , 1, 0, 0, 0, 0, 1, 0, 0, \
76 X(Reg_s5, 5, "s5", 1, 0, 0, 0, 0, 1, 0, 0) \ 93 ALIASES3(Reg_s2 , Reg_d1 , Reg_q0)) \
77 X(Reg_s6, 6, "s6", 1, 0, 0, 0, 0, 1, 0, 0) \ 94 X(Reg_s3 , 3 , "s3" , 1, 0, 0, 0, 0, 1, 0, 0, \
78 X(Reg_s7, 7, "s7", 1, 0, 0, 0, 0, 1, 0, 0) \ 95 ALIASES3(Reg_s3 , Reg_d1 , Reg_q0)) \
79 X(Reg_s8, 8, "s8", 1, 0, 0, 0, 0, 1, 0, 0) \ 96 X(Reg_s4 , 4 , "s4" , 1, 0, 0, 0, 0, 1, 0, 0, \
80 X(Reg_s9, 9, "s9", 1, 0, 0, 0, 0, 1, 0, 0) \ 97 ALIASES3(Reg_s4 , Reg_d2 , Reg_q1)) \
81 X(Reg_s10, 10, "s10", 1, 0, 0, 0, 0, 1, 0, 0) \ 98 X(Reg_s5 , 5 , "s5" , 1, 0, 0, 0, 0, 1, 0, 0, \
82 X(Reg_s11, 11, "s11", 1, 0, 0, 0, 0, 1, 0, 0) \ 99 ALIASES3(Reg_s5 , Reg_d2 , Reg_q1)) \
83 X(Reg_s12, 12, "s12", 1, 0, 0, 0, 0, 1, 0, 0) \ 100 X(Reg_s6 , 6 , "s6" , 1, 0, 0, 0, 0, 1, 0, 0, \
84 X(Reg_s13, 13, "s13", 1, 0, 0, 0, 0, 1, 0, 0) \ 101 ALIASES3(Reg_s6 , Reg_d3 , Reg_q1)) \
85 X(Reg_s14, 14, "s14", 1, 0, 0, 0, 0, 1, 0, 0) \ 102 X(Reg_s7 , 7 , "s7" , 1, 0, 0, 0, 0, 1, 0, 0, \
86 X(Reg_s15, 15, "s15", 1, 0, 0, 0, 0, 1, 0, 0) \ 103 ALIASES3(Reg_s7 , Reg_d3 , Reg_q1)) \
87 X(Reg_s16, 16, "s16", 0, 1, 0, 0, 0, 1, 0, 0) \ 104 X(Reg_s8 , 8 , "s8" , 1, 0, 0, 0, 0, 1, 0, 0, \
88 X(Reg_s17, 17, "s17", 0, 1, 0, 0, 0, 1, 0, 0) \ 105 ALIASES3(Reg_s8 , Reg_d4 , Reg_q2)) \
89 X(Reg_s18, 18, "s18", 0, 1, 0, 0, 0, 1, 0, 0) \ 106 X(Reg_s9 , 9 , "s9" , 1, 0, 0, 0, 0, 1, 0, 0, \
90 X(Reg_s19, 19, "s19", 0, 1, 0, 0, 0, 1, 0, 0) \ 107 ALIASES3(Reg_s9 , Reg_d4 , Reg_q2)) \
91 X(Reg_s20, 20, "s20", 0, 1, 0, 0, 0, 1, 0, 0) \ 108 X(Reg_s10, 10, "s10", 1, 0, 0, 0, 0, 1, 0, 0, \
92 X(Reg_s21, 21, "s21", 0, 1, 0, 0, 0, 1, 0, 0) \ 109 ALIASES3(Reg_s10, Reg_d5 , Reg_q2)) \
93 X(Reg_s22, 22, "s22", 0, 1, 0, 0, 0, 1, 0, 0) \ 110 X(Reg_s11, 11, "s11", 1, 0, 0, 0, 0, 1, 0, 0, \
94 X(Reg_s23, 23, "s23", 0, 1, 0, 0, 0, 1, 0, 0) \ 111 ALIASES3(Reg_s11, Reg_d5 , Reg_q2)) \
95 X(Reg_s24, 24, "s24", 0, 1, 0, 0, 0, 1, 0, 0) \ 112 X(Reg_s12, 12, "s12", 1, 0, 0, 0, 0, 1, 0, 0, \
96 X(Reg_s25, 25, "s25", 0, 1, 0, 0, 0, 1, 0, 0) \ 113 ALIASES3(Reg_s12, Reg_d6 , Reg_q3)) \
97 X(Reg_s26, 26, "s26", 0, 1, 0, 0, 0, 1, 0, 0) \ 114 X(Reg_s13, 13, "s13", 1, 0, 0, 0, 0, 1, 0, 0, \
98 X(Reg_s27, 27, "s27", 0, 1, 0, 0, 0, 1, 0, 0) \ 115 ALIASES3(Reg_s13, Reg_d6 , Reg_q3)) \
99 X(Reg_s28, 28, "s28", 0, 1, 0, 0, 0, 1, 0, 0) \ 116 X(Reg_s14, 14, "s14", 1, 0, 0, 0, 0, 1, 0, 0, \
100 X(Reg_s29, 29, "s29", 0, 1, 0, 0, 0, 1, 0, 0) \ 117 ALIASES3(Reg_s14, Reg_d7 , Reg_q3)) \
101 X(Reg_s30, 30, "s30", 0, 1, 0, 0, 0, 1, 0, 0) \ 118 X(Reg_s15, 15, "s15", 1, 0, 0, 0, 0, 1, 0, 0, \
102 X(Reg_s31, 31, "s31", 0, 1, 0, 0, 0, 1, 0, 0) 119 ALIASES3(Reg_s15, Reg_d7 , Reg_q3)) \
120 X(Reg_s16, 16, "s16", 0, 1, 0, 0, 0, 1, 0, 0, \
121 ALIASES3(Reg_s16, Reg_d8 , Reg_q4)) \
122 X(Reg_s17, 17, "s17", 0, 1, 0, 0, 0, 1, 0, 0, \
123 ALIASES3(Reg_s17, Reg_d8 , Reg_q4)) \
124 X(Reg_s18, 18, "s18", 0, 1, 0, 0, 0, 1, 0, 0, \
125 ALIASES3(Reg_s18, Reg_d9 , Reg_q4)) \
126 X(Reg_s19, 19, "s19", 0, 1, 0, 0, 0, 1, 0, 0, \
127 ALIASES3(Reg_s19, Reg_d9 , Reg_q4)) \
128 X(Reg_s20, 20, "s20", 0, 1, 0, 0, 0, 1, 0, 0, \
129 ALIASES3(Reg_s20, Reg_d10, Reg_q5)) \
130 X(Reg_s21, 21, "s21", 0, 1, 0, 0, 0, 1, 0, 0, \
131 ALIASES3(Reg_s21, Reg_d10, Reg_q5)) \
132 X(Reg_s22, 22, "s22", 0, 1, 0, 0, 0, 1, 0, 0, \
133 ALIASES3(Reg_s22, Reg_d11, Reg_q5)) \
134 X(Reg_s23, 23, "s23", 0, 1, 0, 0, 0, 1, 0, 0, \
135 ALIASES3(Reg_s23, Reg_d11, Reg_q5)) \
136 X(Reg_s24, 24, "s24", 0, 1, 0, 0, 0, 1, 0, 0, \
137 ALIASES3(Reg_s24, Reg_d12, Reg_q6)) \
138 X(Reg_s25, 25, "s25", 0, 1, 0, 0, 0, 1, 0, 0, \
139 ALIASES3(Reg_s25, Reg_d12, Reg_q6)) \
140 X(Reg_s26, 26, "s26", 0, 1, 0, 0, 0, 1, 0, 0, \
141 ALIASES3(Reg_s26, Reg_d13, Reg_q6)) \
142 X(Reg_s27, 27, "s27", 0, 1, 0, 0, 0, 1, 0, 0, \
143 ALIASES3(Reg_s27, Reg_d13, Reg_q6)) \
144 X(Reg_s28, 28, "s28", 0, 1, 0, 0, 0, 1, 0, 0, \
145 ALIASES3(Reg_s28, Reg_d14, Reg_q7)) \
146 X(Reg_s29, 29, "s29", 0, 1, 0, 0, 0, 1, 0, 0, \
147 ALIASES3(Reg_s29, Reg_d14, Reg_q7)) \
148 X(Reg_s30, 30, "s30", 0, 1, 0, 0, 0, 1, 0, 0, \
149 ALIASES3(Reg_s30, Reg_d15, Reg_q7)) \
150 X(Reg_s31, 31, "s31", 0, 1, 0, 0, 0, 1, 0, 0, \
151 ALIASES3(Reg_s31, Reg_d15, Reg_q7))
103 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 152 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
104 // isInt, isFP32, isFP64, isVec128) 153 // isInt, isFP32,isFP64, isVec128, aliases_init)
105 154
106 // D registers 0-7 are scratch, 8-15 are preserved, and 16-31 155 // D registers 0-7 are scratch, 8-15 are preserved, and 16-31
107 // are also scratch (if supported by the D32 feature vs D16). 156 // are also scratch (if supported by the D32 feature vs D16).
157 // D registers are defined in reverse order so that, during register allocation,
158 // Subzero will prefer higher D registers. In processors supporting the D32
159 // feature this will effectively cause double allocation to bias towards
160 // allocating "high" D registers, which do not alias any S registers.
108 // 161 //
109 // Regenerate this with the following python script: 162 // Regenerate this with the following python script:
110 // def print_dregs(): 163 // def print_dregs():
111 // for i in xrange(0, 32): 164 // for i in xrange(31, 15, -1):
112 // is_scratch = 1 if (i < 8 or i >= 16) else 0 165 // is_scratch = 1 if (i < 8 or i >= 16) else 0
113 // is_preserved = 1 if (8 <= i and i < 16) else 0 166 // is_preserved = 1 if (8 <= i and i < 16) else 0
114 // print ('X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' + 167 // print (' X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' +
115 // '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0) \\').format( 168 // '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0, ' +
116 // regnum=i, scratch=is_scratch, preserved=is_preserved) 169 // 'ALIASES(Reg_d{regnum:<2}, Reg_q{regnum_q:<2}) \\').format(
170 // regnum=i, regnum_q=i>>1, scratch=is_scratch,
171 // preserved=is_preserved)
172 // for i in xrange(15, -1, -1):
173 // is_scratch = 1 if (i < 8 or i >= 16) else 0
174 // is_preserved = 1 if (8 <= i and i < 16) else 0
175 // print (' X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' +
176 // '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0, ' +
177 // 'ALIASES(Reg_s{regnum_s0:<2}, Reg_s{regnum_s1:<2}, ' +
178 // 'Reg_d{regnum:<2}, Reg_q{regnum_q:<2})) \\').format(
179 // regnum_s0 = (i<<1), regnum_s1 = (i<<1) + 1, regnum=i,
180 // regnum_q=i>>1, scratch=is_scratch, preserved=is_preserved)
117 // 181 //
118 // print_dregs() 182 // print_dregs()
119 // 183 //
120 #define REGARM32_FP64_TABLE \ 184 #define REGARM32_FP64_TABLE \
121 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 185 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
122 isInt, isFP32, isFP64, isVec128 */ \ 186 isInt, isFP32, isFP64, isVec128, aliases_init */ \
123 X(Reg_d0, 0, "d0", 1, 0, 0, 0, 0, 0, 1, 0) \ 187 X(Reg_d31, 31, "d31", 1, 0, 0, 0, 0, 0, 1, 0, \
124 X(Reg_d1, 1, "d1", 1, 0, 0, 0, 0, 0, 1, 0) \ 188 ALIASES2(Reg_d31, Reg_q15)) \
125 X(Reg_d2, 2, "d2", 1, 0, 0, 0, 0, 0, 1, 0) \ 189 X(Reg_d30, 30, "d30", 1, 0, 0, 0, 0, 0, 1, 0, \
126 X(Reg_d3, 3, "d3", 1, 0, 0, 0, 0, 0, 1, 0) \ 190 ALIASES2(Reg_d30, Reg_q15)) \
127 X(Reg_d4, 4, "d4", 1, 0, 0, 0, 0, 0, 1, 0) \ 191 X(Reg_d29, 29, "d29", 1, 0, 0, 0, 0, 0, 1, 0, \
128 X(Reg_d5, 5, "d5", 1, 0, 0, 0, 0, 0, 1, 0) \ 192 ALIASES2(Reg_d29, Reg_q14)) \
129 X(Reg_d6, 6, "d6", 1, 0, 0, 0, 0, 0, 1, 0) \ 193 X(Reg_d28, 28, "d28", 1, 0, 0, 0, 0, 0, 1, 0, \
130 X(Reg_d7, 7, "d7", 1, 0, 0, 0, 0, 0, 1, 0) \ 194 ALIASES2(Reg_d28, Reg_q14)) \
131 X(Reg_d8, 8, "d8", 0, 1, 0, 0, 0, 0, 1, 0) \ 195 X(Reg_d27, 27, "d27", 1, 0, 0, 0, 0, 0, 1, 0, \
132 X(Reg_d9, 9, "d9", 0, 1, 0, 0, 0, 0, 1, 0) \ 196 ALIASES2(Reg_d27, Reg_q13)) \
133 X(Reg_d10, 10, "d10", 0, 1, 0, 0, 0, 0, 1, 0) \ 197 X(Reg_d26, 26, "d26", 1, 0, 0, 0, 0, 0, 1, 0, \
134 X(Reg_d11, 11, "d11", 0, 1, 0, 0, 0, 0, 1, 0) \ 198 ALIASES2(Reg_d26, Reg_q13)) \
135 X(Reg_d12, 12, "d12", 0, 1, 0, 0, 0, 0, 1, 0) \ 199 X(Reg_d25, 25, "d25", 1, 0, 0, 0, 0, 0, 1, 0, \
136 X(Reg_d13, 13, "d13", 0, 1, 0, 0, 0, 0, 1, 0) \ 200 ALIASES2(Reg_d25, Reg_q12)) \
137 X(Reg_d14, 14, "d14", 0, 1, 0, 0, 0, 0, 1, 0) \ 201 X(Reg_d24, 24, "d24", 1, 0, 0, 0, 0, 0, 1, 0, \
138 X(Reg_d15, 15, "d15", 0, 1, 0, 0, 0, 0, 1, 0) \ 202 ALIASES2(Reg_d24, Reg_q12)) \
139 X(Reg_d16, 16, "d16", 1, 0, 0, 0, 0, 0, 1, 0) \ 203 X(Reg_d23, 23, "d23", 1, 0, 0, 0, 0, 0, 1, 0, \
140 X(Reg_d17, 17, "d17", 1, 0, 0, 0, 0, 0, 1, 0) \ 204 ALIASES2(Reg_d23, Reg_q11)) \
141 X(Reg_d18, 18, "d18", 1, 0, 0, 0, 0, 0, 1, 0) \ 205 X(Reg_d22, 22, "d22", 1, 0, 0, 0, 0, 0, 1, 0, \
142 X(Reg_d19, 19, "d19", 1, 0, 0, 0, 0, 0, 1, 0) \ 206 ALIASES2(Reg_d22, Reg_q11)) \
143 X(Reg_d20, 20, "d20", 1, 0, 0, 0, 0, 0, 1, 0) \ 207 X(Reg_d21, 21, "d21", 1, 0, 0, 0, 0, 0, 1, 0, \
144 X(Reg_d21, 21, "d21", 1, 0, 0, 0, 0, 0, 1, 0) \ 208 ALIASES2(Reg_d21, Reg_q10)) \
145 X(Reg_d22, 22, "d22", 1, 0, 0, 0, 0, 0, 1, 0) \ 209 X(Reg_d20, 20, "d20", 1, 0, 0, 0, 0, 0, 1, 0, \
146 X(Reg_d23, 23, "d23", 1, 0, 0, 0, 0, 0, 1, 0) \ 210 ALIASES2(Reg_d20, Reg_q10)) \
147 X(Reg_d24, 24, "d24", 1, 0, 0, 0, 0, 0, 1, 0) \ 211 X(Reg_d19, 19, "d19", 1, 0, 0, 0, 0, 0, 1, 0, \
148 X(Reg_d25, 25, "d25", 1, 0, 0, 0, 0, 0, 1, 0) \ 212 ALIASES2(Reg_d19, Reg_q9)) \
149 X(Reg_d26, 26, "d26", 1, 0, 0, 0, 0, 0, 1, 0) \ 213 X(Reg_d18, 18, "d18", 1, 0, 0, 0, 0, 0, 1, 0, \
150 X(Reg_d27, 27, "d27", 1, 0, 0, 0, 0, 0, 1, 0) \ 214 ALIASES2(Reg_d18, Reg_q9)) \
151 X(Reg_d28, 28, "d28", 1, 0, 0, 0, 0, 0, 1, 0) \ 215 X(Reg_d17, 17, "d17", 1, 0, 0, 0, 0, 0, 1, 0, \
152 X(Reg_d29, 29, "d29", 1, 0, 0, 0, 0, 0, 1, 0) \ 216 ALIASES2(Reg_d17, Reg_q8)) \
153 X(Reg_d30, 30, "d30", 1, 0, 0, 0, 0, 0, 1, 0) \ 217 X(Reg_d16, 16, "d16", 1, 0, 0, 0, 0, 0, 1, 0, \
154 X(Reg_d31, 31, "d31", 1, 0, 0, 0, 0, 0, 1, 0) 218 ALIASES2(Reg_d16, Reg_q8)) \
219 X(Reg_d15, 15, "d15", 0, 1, 0, 0, 0, 0, 1, 0, \
220 ALIASES4(Reg_s30, Reg_s31, Reg_d15, Reg_q7)) \
221 X(Reg_d14, 14, "d14", 0, 1, 0, 0, 0, 0, 1, 0, \
222 ALIASES4(Reg_s28, Reg_s29, Reg_d14, Reg_q7)) \
223 X(Reg_d13, 13, "d13", 0, 1, 0, 0, 0, 0, 1, 0, \
224 ALIASES4(Reg_s26, Reg_s27, Reg_d13, Reg_q6)) \
225 X(Reg_d12, 12, "d12", 0, 1, 0, 0, 0, 0, 1, 0, \
226 ALIASES4(Reg_s24, Reg_s25, Reg_d12, Reg_q6)) \
227 X(Reg_d11, 11, "d11", 0, 1, 0, 0, 0, 0, 1, 0, \
228 ALIASES4(Reg_s22, Reg_s23, Reg_d11, Reg_q5)) \
229 X(Reg_d10, 10, "d10", 0, 1, 0, 0, 0, 0, 1, 0, \
230 ALIASES4(Reg_s20, Reg_s21, Reg_d10, Reg_q5)) \
231 X(Reg_d9 , 9 , "d9", 0, 1, 0, 0, 0, 0, 1, 0, \
232 ALIASES4(Reg_s18, Reg_s19, Reg_d9 , Reg_q4)) \
233 X(Reg_d8 , 8 , "d8", 0, 1, 0, 0, 0, 0, 1, 0, \
234 ALIASES4(Reg_s16, Reg_s17, Reg_d8 , Reg_q4)) \
235 X(Reg_d7 , 7 , "d7", 1, 0, 0, 0, 0, 0, 1, 0, \
236 ALIASES4(Reg_s14, Reg_s15, Reg_d7 , Reg_q3)) \
237 X(Reg_d6 , 6 , "d6", 1, 0, 0, 0, 0, 0, 1, 0, \
238 ALIASES4(Reg_s12, Reg_s13, Reg_d6 , Reg_q3)) \
239 X(Reg_d5 , 5 , "d5", 1, 0, 0, 0, 0, 0, 1, 0, \
240 ALIASES4(Reg_s10, Reg_s11, Reg_d5 , Reg_q2)) \
241 X(Reg_d4 , 4 , "d4", 1, 0, 0, 0, 0, 0, 1, 0, \
242 ALIASES4(Reg_s8 , Reg_s9 , Reg_d4 , Reg_q2)) \
243 X(Reg_d3 , 3 , "d3", 1, 0, 0, 0, 0, 0, 1, 0, \
244 ALIASES4(Reg_s6 , Reg_s7 , Reg_d3 , Reg_q1)) \
245 X(Reg_d2 , 2 , "d2", 1, 0, 0, 0, 0, 0, 1, 0, \
246 ALIASES4(Reg_s4 , Reg_s5 , Reg_d2 , Reg_q1)) \
247 X(Reg_d1 , 1 , "d1", 1, 0, 0, 0, 0, 0, 1, 0, \
248 ALIASES4(Reg_s2 , Reg_s3 , Reg_d1 , Reg_q0)) \
249 X(Reg_d0 , 0 , "d0", 1, 0, 0, 0, 0, 0, 1, 0, \
250 ALIASES4(Reg_s0 , Reg_s1 , Reg_d0 , Reg_q0))
155 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 251 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
156 // isInt, isFP32, isFP64, isVec128) 252 // isInt, isFP32, isFP64, isVec128, aliases_init)
157 253
158 // Q registers 0-3 are scratch, 4-7 are preserved, and 8-15 254 // Q registers 0-3 are scratch, 4-7 are preserved, and 8-15
159 // are also scratch (if supported by the D32 feature). 255 // are also scratch (if supported by the D32 feature).
256 // Q registers are defined in reverse order for the same reason as D registers.
160 // 257 //
161 // Regenerate this with the following python script: 258 // Regenerate this with the following python script:
162 // def print_qregs(): 259 // def print_qregs():
163 // for i in xrange(0, 16): 260 // for i in xrange(15, 7, -1):
164 // is_scratch = 1 if (i < 4 or i >= 8) else 0 261 // is_scratch = 1 if (i < 4 or i >= 8) else 0
165 // is_preserved = 1 if (4 <= i and i < 8) else 0 262 // is_preserved = 1 if (4 <= i and i < 8) else 0
166 // print ('X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' + 263 // print (' X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' +
167 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1) \\').format( 264 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, ALIASES(' +
265 // 'Reg_d{regnum_d0:<2}, Reg_d{regnum_d1:<2}, ' +
266 // 'Reg_q{regnum:<2})) \\').format(
267 // regnum_d0=(i<<1), regnum_d1=(i<<1)+1, regnum=i,
268 // scratch=is_scratch, preserved=is_preserved)
269 // for i in xrange(7, -1, -1):
270 // is_scratch = 1 if (i < 4 or i >= 8) else 0
271 // is_preserved = 1 if (4 <= i and i < 8) else 0
272 // print (' X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' +
273 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, ALIASES(' +
274 // 'Reg_s{regnum_s0:<2}, Reg_s{regnum_s1:<2}, ' +
275 // 'Reg_s{regnum_s2:<2}, Reg_s{regnum_s3:<2}, ' +
276 // 'Reg_d{regnum_d0:<2}, Reg_d{regnum_d1:<2}, ' +
277 // 'Reg_q{regnum:<2})) \\').format(
278 // regnum_s0=(i<<2), regnum_s1=(i<<2)+1, regnum_s2=(i<<2)+2,
279 // regnum_s3=(i<<2)+3, regnum_d0=(i<<1), regnum_d1=(i<<1)+1,
168 // regnum=i, scratch=is_scratch, preserved=is_preserved) 280 // regnum=i, scratch=is_scratch, preserved=is_preserved)
169 // 281 //
170 // print_qregs() 282 // print_qregs()
171 // 283 //
172 #define REGARM32_VEC128_TABLE \ 284 #define REGARM32_VEC128_TABLE \
173 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 285 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
174 isInt, isFP32, isFP64, isVec128 */ \ 286 isInt, isFP32, isFP64, isVec128, alias_init */ \
175 X(Reg_q0, 0, "q0", 1, 0, 0, 0, 0, 0, 0, 1) \ 287 X(Reg_q15, 15, "q15", 1, 0, 0, 0, 0, 0, 0, 1, \
176 X(Reg_q1, 1, "q1", 1, 0, 0, 0, 0, 0, 0, 1) \ 288 ALIASES3(Reg_d30, Reg_d31, Reg_q15)) \
177 X(Reg_q2, 2, "q2", 1, 0, 0, 0, 0, 0, 0, 1) \ 289 X(Reg_q14, 14, "q14", 1, 0, 0, 0, 0, 0, 0, 1, \
178 X(Reg_q3, 3, "q3", 1, 0, 0, 0, 0, 0, 0, 1) \ 290 ALIASES3(Reg_d28, Reg_d29, Reg_q14)) \
179 X(Reg_q4, 4, "q4", 0, 1, 0, 0, 0, 0, 0, 1) \ 291 X(Reg_q13, 13, "q13", 1, 0, 0, 0, 0, 0, 0, 1, \
180 X(Reg_q5, 5, "q5", 0, 1, 0, 0, 0, 0, 0, 1) \ 292 ALIASES3(Reg_d26, Reg_d27, Reg_q13)) \
181 X(Reg_q6, 6, "q6", 0, 1, 0, 0, 0, 0, 0, 1) \ 293 X(Reg_q12, 12, "q12", 1, 0, 0, 0, 0, 0, 0, 1, \
182 X(Reg_q7, 7, "q7", 0, 1, 0, 0, 0, 0, 0, 1) \ 294 ALIASES3(Reg_d24, Reg_d25, Reg_q12)) \
183 X(Reg_q8, 8, "q8", 1, 0, 0, 0, 0, 0, 0, 1) \ 295 X(Reg_q11, 11, "q11", 1, 0, 0, 0, 0, 0, 0, 1, \
184 X(Reg_q9, 9, "q9", 1, 0, 0, 0, 0, 0, 0, 1) \ 296 ALIASES3(Reg_d22, Reg_d23, Reg_q11)) \
185 X(Reg_q10, 10, "q10", 1, 0, 0, 0, 0, 0, 0, 1) \ 297 X(Reg_q10, 10, "q10", 1, 0, 0, 0, 0, 0, 0, 1, \
186 X(Reg_q11, 11, "q11", 1, 0, 0, 0, 0, 0, 0, 1) \ 298 ALIASES3(Reg_d20, Reg_d21, Reg_q10)) \
187 X(Reg_q12, 12, "q12", 1, 0, 0, 0, 0, 0, 0, 1) \ 299 X(Reg_q9 , 9 , "q9", 1, 0, 0, 0, 0, 0, 0, 1, \
188 X(Reg_q13, 13, "q13", 1, 0, 0, 0, 0, 0, 0, 1) \ 300 ALIASES3(Reg_d18, Reg_d19, Reg_q9)) \
189 X(Reg_q14, 14, "q14", 1, 0, 0, 0, 0, 0, 0, 1) \ 301 X(Reg_q8 , 8 , "q8", 1, 0, 0, 0, 0, 0, 0, 1, \
190 X(Reg_q15, 15, "q15", 1, 0, 0, 0, 0, 0, 0, 1) 302 ALIASES3(Reg_d16, Reg_d17, Reg_q8)) \
303 X(Reg_q7 , 7 , "q7", 0, 1, 0, 0, 0, 0, 0, 1, \
304 ALIASES7(Reg_s28, Reg_s29, Reg_s30, Reg_s31, Reg_d14, Reg_d15, Reg_q7)) \
305 X(Reg_q6 , 6 , "q6", 0, 1, 0, 0, 0, 0, 0, 1, \
306 ALIASES7(Reg_s24, Reg_s25, Reg_s26, Reg_s27, Reg_d12, Reg_d13, Reg_q6)) \
307 X(Reg_q5 , 5 , "q5", 0, 1, 0, 0, 0, 0, 0, 1, \
308 ALIASES7(Reg_s20, Reg_s21, Reg_s22, Reg_s23, Reg_d10, Reg_d11, Reg_q5)) \
309 X(Reg_q4 , 4 , "q4", 0, 1, 0, 0, 0, 0, 0, 1, \
310 ALIASES7(Reg_s16, Reg_s17, Reg_s18, Reg_s19, Reg_d8 , Reg_d9 , Reg_q4)) \
311 X(Reg_q3 , 3 , "q3", 1, 0, 0, 0, 0, 0, 0, 1, \
312 ALIASES7(Reg_s12, Reg_s13, Reg_s14, Reg_s15, Reg_d6 , Reg_d7 , Reg_q3)) \
313 X(Reg_q2 , 2 , "q2", 1, 0, 0, 0, 0, 0, 0, 1, \
314 ALIASES7(Reg_s8 , Reg_s9 , Reg_s10, Reg_s11, Reg_d4 , Reg_d5 , Reg_q2)) \
315 X(Reg_q1 , 1 , "q1", 1, 0, 0, 0, 0, 0, 0, 1, \
316 ALIASES7(Reg_s4 , Reg_s5 , Reg_s6 , Reg_s7 , Reg_d2 , Reg_d3 , Reg_q1)) \
317 X(Reg_q0 , 0 , "q0", 1, 0, 0, 0, 0, 0, 0, 1, \
318 ALIASES7(Reg_s0 , Reg_s1 , Reg_s2 , Reg_s3 , Reg_d0 , Reg_d1 , Reg_q0))
191 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 319 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
192 // isInt, isFP32, isFP64, isVec128) 320 // isInt, isFP32, isFP64, isVec128, alias_init)
321 #undef ALIASES
193 322
194 // We also provide a combined table, so that there is a namespace where 323 // We also provide a combined table, so that there is a namespace where
195 // all of the registers are considered and have distinct numberings. 324 // all of the registers are considered and have distinct numberings.
196 // This is in contrast to the above, where the "encode" is based on how 325 // This is in contrast to the above, where the "encode" is based on how
197 // the register numbers will be encoded in binaries and values can overlap. 326 // the register numbers will be encoded in binaries and values can overlap.
198 #define REGARM32_TABLE \ 327 #define REGARM32_TABLE \
199 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ 328 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
200 isFP32, isFP64, isVec128 */ \ 329 isFP32, isFP64, isVec128, alias_init */ \
201 REGARM32_GPR_TABLE \ 330 REGARM32_GPR_TABLE \
202 REGARM32_FP32_TABLE \ 331 REGARM32_FP32_TABLE \
203 REGARM32_FP64_TABLE \ 332 REGARM32_FP64_TABLE \
204 REGARM32_VEC128_TABLE 333 REGARM32_VEC128_TABLE
205 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 334 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
206 // isInt, isFP32, isFP64, isVec128) 335 // isInt, isFP32, isFP64, isVec128, alias_init)
207 336
208 #define REGARM32_TABLE_BOUNDS \ 337 #define REGARM32_TABLE_BOUNDS \
209 /* val, init */ \ 338 /* val, init */ \
210 X(Reg_GPR_First, = Reg_r0) \ 339 X(Reg_GPR_First, = Reg_r0) \
211 X(Reg_GPR_Last, = Reg_pc) \ 340 X(Reg_GPR_Last, = Reg_pc) \
212 X(Reg_SREG_First, = Reg_s0) \ 341 X(Reg_SREG_First, = Reg_s0) \
213 X(Reg_SREG_Last, = Reg_s31) \ 342 X(Reg_SREG_Last, = Reg_s31) \
214 X(Reg_DREG_First, = Reg_d0) \ 343 X(Reg_DREG_First, = Reg_d0) \
215 X(Reg_DREG_Last, = Reg_d31) \ 344 X(Reg_DREG_Last, = Reg_d31) \
216 X(Reg_QREG_First, = Reg_q0) \ 345 X(Reg_QREG_First, = Reg_q0) \
217 X(Reg_QREG_Last, = Reg_q15) 346 X(Reg_QREG_Last, = Reg_q15)
218 // define X(val, init) 347 // define X(val, init)
219 348
220 // Load/Store instruction width suffixes and FP/Vector element size suffixes 349 // Load/Store instruction width suffixes and FP/Vector element size suffixes
221 // the # of offset bits allowed as part of an addressing mode (for sign or 350 // the # of offset bits allowed as part of an addressing mode (for sign or
222 // zero extending load/stores). 351 // zero extending load/stores).
223 #define ICETYPEARM32_TABLE \ 352 #define ICETYPEARM32_TABLE \
224 /* tag, element type, int_width, vec_width, addr bits sext, zext */ \ 353 /* tag, element type, int_width, vec_width, addr bits sext, zext */ \
225 X(IceType_void, IceType_void, "", "", 0, 0) \ 354 X(IceType_void, IceType_void, "" , "" , 0 , 0) \
226 X(IceType_i1, IceType_void, "b", "", 8, 12) \ 355 X(IceType_i1, IceType_void, "b", "" , 8 , 12) \
227 X(IceType_i8, IceType_void, "b", "", 8, 12) \ 356 X(IceType_i8, IceType_void, "b", "" , 8 , 12) \
228 X(IceType_i16, IceType_void, "h", "", 8, 8) \ 357 X(IceType_i16, IceType_void, "h", "" , 8 , 8) \
229 X(IceType_i32, IceType_void, "", "", 12, 12) \ 358 X(IceType_i32, IceType_void, "" , "" , 12, 12) \
230 X(IceType_i64, IceType_void, "d", "", 8, 8) \ 359 X(IceType_i64, IceType_void, "d", "" , 8 , 8) \
231 X(IceType_f32, IceType_void, "", ".f32", 10, 10) \ 360 X(IceType_f32, IceType_void, "" , ".f32", 10, 10) \
232 X(IceType_f64, IceType_void, "", ".f64", 10, 10) \ 361 X(IceType_f64, IceType_void, "" , ".f64", 10, 10) \
233 X(IceType_v4i1, IceType_i32, "", ".i32", 0, 0) \ 362 X(IceType_v4i1, IceType_i32 , "" , ".i32", 0 , 0) \
234 X(IceType_v8i1, IceType_i16, "", ".i16", 0, 0) \ 363 X(IceType_v8i1, IceType_i16 , "" , ".i16", 0 , 0) \
235 X(IceType_v16i1, IceType_i8, "", ".i8", 0, 0) \ 364 X(IceType_v16i1, IceType_i8 , "" , ".i8" , 0 , 0) \
236 X(IceType_v16i8, IceType_i8, "", ".i8", 0, 0) \ 365 X(IceType_v16i8, IceType_i8 , "" , ".i8" , 0 , 0) \
237 X(IceType_v8i16, IceType_i16, "", ".i16", 0, 0) \ 366 X(IceType_v8i16, IceType_i16 , "" , ".i16", 0 , 0) \
238 X(IceType_v4i32, IceType_i32, "", ".i32", 0, 0) \ 367 X(IceType_v4i32, IceType_i32 , "" , ".i32", 0 , 0) \
239 X(IceType_v4f32, IceType_f32, "", ".f32", 0, 0) 368 X(IceType_v4f32, IceType_f32 , "" , ".f32", 0 , 0)
240 //#define X(tag, elementty, int_width, vec_width, sbits, ubits) 369 //#define X(tag, elementty, int_width, vec_width, sbits, ubits)
241 370
242 // Shifter types for Data-processing operands as defined in section A5.1.2. 371 // Shifter types for Data-processing operands as defined in section A5.1.2.
243 #define ICEINSTARM32SHIFT_TABLE \ 372 #define ICEINSTARM32SHIFT_TABLE \
244 /* enum value, emit */ \ 373 /* enum value, emit */ \
245 X(LSL, "lsl") \ 374 X(LSL, "lsl") \
246 X(LSR, "lsr") \ 375 X(LSR, "lsr") \
247 X(ASR, "asr") \ 376 X(ASR, "asr") \
248 X(ROR, "ror") \ 377 X(ROR, "ror") \
249 X(RRX, "rrx") 378 X(RRX, "rrx")
250 //#define X(tag, emit) 379 //#define X(tag, emit)
251 380
252 // Attributes for the condition code 4-bit encoding (that is independent 381 // Attributes for the condition code 4-bit encoding (that is independent
253 // of the APSR's NZCV fields). For example, EQ is 0, but corresponds to 382 // of the APSR's NZCV fields). For example, EQ is 0, but corresponds to
254 // Z = 1, and NE is 1, but corresponds to Z = 0. 383 // Z = 1, and NE is 1, but corresponds to Z = 0.
255 #define ICEINSTARM32COND_TABLE \ 384 #define ICEINSTARM32COND_TABLE \
256 /* enum value, encoding, opposite, emit */ \ 385 /* enum value, encoding, opposite, emit */ \
257 X(EQ, 0, NE, "eq") /* equal */ \ 386 X(EQ, 0 , NE, "eq") /* equal */ \
258 X(NE, 1, EQ, "ne") /* not equal */ \ 387 X(NE, 1 , EQ, "ne") /* not equal */ \
259 X(CS, 2, CC, "cs") /* carry set/unsigned (AKA hs: higher or same) */ \ 388 X(CS, 2 , CC, "cs") /* carry set/unsigned (AKA hs: higher or same) */ \
260 X(CC, 3, CS, "cc") /* carry clear/unsigned (AKA lo: lower) */ \ 389 X(CC, 3 , CS, "cc") /* carry clear/unsigned (AKA lo: lower) */ \
261 X(MI, 4, PL, "mi") /* minus/negative */ \ 390 X(MI, 4 , PL, "mi") /* minus/negative */ \
262 X(PL, 5, MI, "pl") /* plus/positive or zero */ \ 391 X(PL, 5 , MI, "pl") /* plus/positive or zero */ \
263 X(VS, 6, VC, "vs") /* overflow (float unordered) */ \ 392 X(VS, 6 , VC, "vs") /* overflow (float unordered) */ \
264 X(VC, 7, VS, "vc") /* no overflow (float not unordered) */ \ 393 X(VC, 7 , VS, "vc") /* no overflow (float not unordered) */ \
265 X(HI, 8, LS, "hi") /* unsigned higher */ \ 394 X(HI, 8 , LS, "hi") /* unsigned higher */ \
266 X(LS, 9, HI, "ls") /* unsigned lower or same */ \ 395 X(LS, 9 , HI, "ls") /* unsigned lower or same */ \
267 X(GE, 10, LT, "ge") /* signed greater than or equal */ \ 396 X(GE, 10, LT, "ge") /* signed greater than or equal */ \
268 X(LT, 11, GE, "lt") /* signed less than */ \ 397 X(LT, 11, GE, "lt") /* signed less than */ \
269 X(GT, 12, LE, "gt") /* signed greater than */ \ 398 X(GT, 12, LE, "gt") /* signed greater than */ \
270 X(LE, 13, GT, "le") /* signed less than or equal */ \ 399 X(LE, 13, GT, "le") /* signed less than or equal */ \
271 X(AL, 14, kNone, "") /* always (unconditional) */ \ 400 X(AL, 14, kNone, "") /* always (unconditional) */ \
272 X(kNone, 15, kNone, "??") /* special condition / none */ 401 X(kNone, 15, kNone, "??") /* special condition / none */
273 //#define(tag, encode, opp, emit) 402 //#define(tag, encode, opp, emit)
274 403
275 #endif // SUBZERO_SRC_ICEINSTARM32_DEF 404 #endif // SUBZERO_SRC_ICEINSTARM32_DEF
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