| Index: source/libvpx/vpx_dsp/vpx_dsp.mk
|
| diff --git a/source/libvpx/vpx_dsp/vpx_dsp.mk b/source/libvpx/vpx_dsp/vpx_dsp.mk
|
| index 4d4059a998a39f348d276b29fc88e558f18f4294..61670d922a7508ae2f0cd2b2fa3ee4f948a15b3b 100644
|
| --- a/source/libvpx/vpx_dsp/vpx_dsp.mk
|
| +++ b/source/libvpx/vpx_dsp/vpx_dsp.mk
|
| @@ -22,6 +22,10 @@ DSP_SRCS-yes += bitwriter.h
|
| DSP_SRCS-yes += bitwriter.c
|
| DSP_SRCS-yes += bitwriter_buffer.c
|
| DSP_SRCS-yes += bitwriter_buffer.h
|
| +DSP_SRCS-$(CONFIG_INTERNAL_STATS) += ssim.c
|
| +DSP_SRCS-$(CONFIG_INTERNAL_STATS) += ssim.h
|
| +DSP_SRCS-$(CONFIG_INTERNAL_STATS) += psnrhvs.c
|
| +DSP_SRCS-$(CONFIG_INTERNAL_STATS) += fastssim.c
|
| endif
|
|
|
| ifeq ($(CONFIG_DECODERS),yes)
|
| @@ -32,16 +36,18 @@ DSP_SRCS-yes += bitreader_buffer.h
|
| endif
|
|
|
| # intra predictions
|
| -ifeq ($(CONFIG_VP9),yes)
|
| +ifneq ($(filter yes,$(CONFIG_VP9) $(CONFIG_VP10)),)
|
| DSP_SRCS-yes += intrapred.c
|
|
|
| ifeq ($(CONFIG_USE_X86INC),yes)
|
| +DSP_SRCS-$(HAVE_SSE) += x86/intrapred_sse2.asm
|
| DSP_SRCS-$(HAVE_SSE2) += x86/intrapred_sse2.asm
|
| DSP_SRCS-$(HAVE_SSSE3) += x86/intrapred_ssse3.asm
|
| endif # CONFIG_USE_X86INC
|
|
|
| ifeq ($(CONFIG_VP9_HIGHBITDEPTH),yes)
|
| ifeq ($(CONFIG_USE_X86INC),yes)
|
| +DSP_SRCS-$(HAVE_SSE) += x86/highbd_intrapred_sse2.asm
|
| DSP_SRCS-$(HAVE_SSE2) += x86/highbd_intrapred_sse2.asm
|
| endif # CONFIG_USE_X86INC
|
| endif # CONFIG_VP9_HIGHBITDEPTH
|
| @@ -52,7 +58,10 @@ DSP_SRCS-$(HAVE_MSA) += mips/intrapred_msa.c
|
| DSP_SRCS-$(HAVE_DSPR2) += mips/intrapred4_dspr2.c
|
| DSP_SRCS-$(HAVE_DSPR2) += mips/intrapred8_dspr2.c
|
| DSP_SRCS-$(HAVE_DSPR2) += mips/intrapred16_dspr2.c
|
| -endif # CONFIG_VP9
|
| +endif # CONFIG_VP9 || CONFIG_VP10
|
| +
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/common_dspr2.h
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/common_dspr2.c
|
|
|
| # interpolation filters
|
| DSP_SRCS-yes += vpx_convolve.c
|
| @@ -103,17 +112,17 @@ DSP_SRCS-$(HAVE_MSA) += mips/vpx_convolve_copy_msa.c
|
| DSP_SRCS-$(HAVE_MSA) += mips/vpx_convolve_msa.h
|
|
|
| # common (dspr2)
|
| -DSP_SRCS-$(HAVE_DSPR2) += mips/vpx_common_dspr2.h
|
| -DSP_SRCS-$(HAVE_DSPR2) += mips/vpx_convolve2_avg_dspr2.c
|
| -DSP_SRCS-$(HAVE_DSPR2) += mips/vpx_convolve2_avg_horiz_dspr2.c
|
| -DSP_SRCS-$(HAVE_DSPR2) += mips/vpx_convolve2_dspr2.c
|
| -DSP_SRCS-$(HAVE_DSPR2) += mips/vpx_convolve2_horiz_dspr2.c
|
| -DSP_SRCS-$(HAVE_DSPR2) += mips/vpx_convolve2_vert_dspr2.c
|
| -DSP_SRCS-$(HAVE_DSPR2) += mips/vpx_convolve8_avg_dspr2.c
|
| -DSP_SRCS-$(HAVE_DSPR2) += mips/vpx_convolve8_avg_horiz_dspr2.c
|
| -DSP_SRCS-$(HAVE_DSPR2) += mips/vpx_convolve8_dspr2.c
|
| -DSP_SRCS-$(HAVE_DSPR2) += mips/vpx_convolve8_horiz_dspr2.c
|
| -DSP_SRCS-$(HAVE_DSPR2) += mips/vpx_convolve8_vert_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/convolve_common_dspr2.h
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/convolve2_avg_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/convolve2_avg_horiz_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/convolve2_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/convolve2_horiz_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/convolve2_vert_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/convolve8_avg_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/convolve8_avg_horiz_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/convolve8_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/convolve8_horiz_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/convolve8_vert_dspr2.c
|
|
|
| # loop filters
|
| DSP_SRCS-yes += loopfilter.c
|
| @@ -140,6 +149,13 @@ DSP_SRCS-$(HAVE_MSA) += mips/loopfilter_msa.h
|
| DSP_SRCS-$(HAVE_MSA) += mips/loopfilter_16_msa.c
|
| DSP_SRCS-$(HAVE_MSA) += mips/loopfilter_8_msa.c
|
| DSP_SRCS-$(HAVE_MSA) += mips/loopfilter_4_msa.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/loopfilter_filters_dspr2.h
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/loopfilter_filters_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/loopfilter_macros_dspr2.h
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/loopfilter_masks_dspr2.h
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/loopfilter_mb_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/loopfilter_mb_horiz_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/loopfilter_mb_vert_dspr2.c
|
|
|
| ifeq ($(CONFIG_VP9_HIGHBITDEPTH),yes)
|
| DSP_SRCS-$(HAVE_SSE2) += x86/highbd_loopfilter_sse2.c
|
| @@ -149,7 +165,7 @@ DSP_SRCS-yes += txfm_common.h
|
| DSP_SRCS-$(HAVE_SSE2) += x86/txfm_common_sse2.h
|
| DSP_SRCS-$(HAVE_MSA) += mips/txfm_macros_msa.h
|
| # forward transform
|
| -ifeq ($(CONFIG_VP9_ENCODER),yes)
|
| +ifneq ($(filter yes,$(CONFIG_VP9_ENCODER) $(CONFIG_VP10_ENCODER)),)
|
| DSP_SRCS-yes += fwd_txfm.c
|
| DSP_SRCS-yes += fwd_txfm.h
|
| DSP_SRCS-$(HAVE_SSE2) += x86/fwd_txfm_sse2.h
|
| @@ -167,22 +183,23 @@ DSP_SRCS-$(HAVE_NEON) += arm/fwd_txfm_neon.c
|
| DSP_SRCS-$(HAVE_MSA) += mips/fwd_txfm_msa.h
|
| DSP_SRCS-$(HAVE_MSA) += mips/fwd_txfm_msa.c
|
| DSP_SRCS-$(HAVE_MSA) += mips/fwd_dct32x32_msa.c
|
| -endif # CONFIG_VP9_ENCODER
|
| +endif # CONFIG_VP9_ENCODER || CONFIG_VP10_ENCODER
|
|
|
| # inverse transform
|
| -ifeq ($(CONFIG_VP9),yes)
|
| +ifneq ($(filter yes,$(CONFIG_VP9) $(CONFIG_VP10)),)
|
| DSP_SRCS-yes += inv_txfm.h
|
| DSP_SRCS-yes += inv_txfm.c
|
| DSP_SRCS-$(HAVE_SSE2) += x86/inv_txfm_sse2.h
|
| DSP_SRCS-$(HAVE_SSE2) += x86/inv_txfm_sse2.c
|
| ifeq ($(CONFIG_USE_X86INC),yes)
|
| -DSP_SRCS-$(HAVE_SSE2) += x86/inv_txfm_sse2.asm
|
| +DSP_SRCS-$(HAVE_SSE2) += x86/inv_wht_sse2.asm
|
| ifeq ($(ARCH_X86_64),yes)
|
| DSP_SRCS-$(HAVE_SSSE3) += x86/inv_txfm_ssse3_x86_64.asm
|
| endif # ARCH_X86_64
|
| endif # CONFIG_USE_X86INC
|
|
|
| ifeq ($(HAVE_NEON_ASM),yes)
|
| +DSP_SRCS-yes += arm/save_reg_neon$(ASM)
|
| DSP_SRCS-yes += arm/idct4x4_1_add_neon$(ASM)
|
| DSP_SRCS-yes += arm/idct4x4_add_neon$(ASM)
|
| DSP_SRCS-yes += arm/idct8x8_1_add_neon$(ASM)
|
| @@ -210,10 +227,19 @@ DSP_SRCS-$(HAVE_MSA) += mips/idct4x4_msa.c
|
| DSP_SRCS-$(HAVE_MSA) += mips/idct8x8_msa.c
|
| DSP_SRCS-$(HAVE_MSA) += mips/idct16x16_msa.c
|
| DSP_SRCS-$(HAVE_MSA) += mips/idct32x32_msa.c
|
| -endif # CONFIG_VP9
|
| +
|
| +ifneq ($(CONFIG_VP9_HIGHBITDEPTH),yes)
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/inv_txfm_dspr2.h
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/itrans4_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/itrans8_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/itrans16_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/itrans32_dspr2.c
|
| +DSP_SRCS-$(HAVE_DSPR2) += mips/itrans32_cols_dspr2.c
|
| +endif # CONFIG_VP9_HIGHBITDEPTH
|
| +endif # CONFIG_VP9 || CONFIG_VP10
|
|
|
| # quantization
|
| -ifeq ($(CONFIG_VP9_ENCODER),yes)
|
| +ifneq ($(filter yes, $(CONFIG_VP9_ENCODER) $(CONFIG_VP10_ENCODER)),)
|
| DSP_SRCS-yes += quantize.c
|
| DSP_SRCS-yes += quantize.h
|
|
|
| @@ -226,7 +252,7 @@ ifeq ($(CONFIG_USE_X86INC),yes)
|
| DSP_SRCS-$(HAVE_SSSE3) += x86/quantize_ssse3_x86_64.asm
|
| endif
|
| endif
|
| -endif # CONFIG_VP9_ENCODER
|
| +endif # CONFIG_VP9_ENCODER || CONFIG_VP10_ENCODER
|
|
|
| ifeq ($(CONFIG_ENCODERS),yes)
|
| DSP_SRCS-yes += sad.c
|
| @@ -248,6 +274,8 @@ DSP_SRCS-$(HAVE_AVX2) += x86/sad4d_avx2.c
|
| DSP_SRCS-$(HAVE_AVX2) += x86/sad_avx2.c
|
|
|
| ifeq ($(CONFIG_USE_X86INC),yes)
|
| +DSP_SRCS-$(HAVE_SSE) += x86/sad4d_sse2.asm
|
| +DSP_SRCS-$(HAVE_SSE) += x86/sad_sse2.asm
|
| DSP_SRCS-$(HAVE_SSE2) += x86/sad4d_sse2.asm
|
| DSP_SRCS-$(HAVE_SSE2) += x86/sad_sse2.asm
|
| DSP_SRCS-$(HAVE_SSE2) += x86/subtract_sse2.asm
|
| @@ -278,13 +306,19 @@ DSP_SRCS-$(HAVE_MSA) += mips/sub_pixel_variance_msa.c
|
|
|
| DSP_SRCS-$(HAVE_MMX) += x86/variance_mmx.c
|
| DSP_SRCS-$(HAVE_MMX) += x86/variance_impl_mmx.asm
|
| +DSP_SRCS-$(HAVE_SSE) += x86/variance_sse2.c
|
| DSP_SRCS-$(HAVE_SSE2) += x86/variance_sse2.c # Contains SSE2 and SSSE3
|
| DSP_SRCS-$(HAVE_SSE2) += x86/halfpix_variance_sse2.c
|
| DSP_SRCS-$(HAVE_SSE2) += x86/halfpix_variance_impl_sse2.asm
|
| DSP_SRCS-$(HAVE_AVX2) += x86/variance_avx2.c
|
| DSP_SRCS-$(HAVE_AVX2) += x86/variance_impl_avx2.c
|
|
|
| +ifeq ($(ARCH_X86_64),yes)
|
| +DSP_SRCS-$(HAVE_SSE2) += x86/ssim_opt_x86_64.asm
|
| +endif # ARCH_X86_64
|
| +
|
| ifeq ($(CONFIG_USE_X86INC),yes)
|
| +DSP_SRCS-$(HAVE_SSE) += x86/subpel_variance_sse2.asm
|
| DSP_SRCS-$(HAVE_SSE2) += x86/subpel_variance_sse2.asm # Contains SSE2 and SSSE3
|
| endif # CONFIG_USE_X86INC
|
|
|
|
|