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Side by Side Diff: source/libvpx/vpx_dsp/mips/itrans32_dspr2.c

Issue 1302353004: libvpx: Pull from upstream (Closed) Base URL: https://chromium.googlesource.com/chromium/deps/libvpx.git@master
Patch Set: Created 5 years, 3 months ago
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1 /* 1 /*
2 * Copyright (c) 2013 The WebM project authors. All Rights Reserved. 2 * Copyright (c) 2013 The WebM project authors. All Rights Reserved.
3 * 3 *
4 * Use of this source code is governed by a BSD-style license 4 * Use of this source code is governed by a BSD-style license
5 * that can be found in the LICENSE file in the root of the source 5 * that can be found in the LICENSE file in the root of the source
6 * tree. An additional intellectual property rights grant can be found 6 * tree. An additional intellectual property rights grant can be found
7 * in the file PATENTS. All contributing project authors may 7 * in the file PATENTS. All contributing project authors may
8 * be found in the AUTHORS file in the root of the source tree. 8 * be found in the AUTHORS file in the root of the source tree.
9 */ 9 */
10 10
11 #include <assert.h> 11 #include <assert.h>
12 #include <stdio.h> 12 #include <stdio.h>
13 13
14 #include "./vpx_config.h" 14 #include "./vpx_config.h"
15 #include "./vp9_rtcd.h" 15 #include "vpx_dsp/mips/inv_txfm_dspr2.h"
16 #include "vp9/common/vp9_common.h"
17 #include "vp9/common/vp9_blockd.h"
18 #include "vp9/common/mips/dspr2/vp9_common_dspr2.h"
19 #include "vpx_dsp/txfm_common.h" 16 #include "vpx_dsp/txfm_common.h"
20 17
21 #if HAVE_DSPR2 18 #if HAVE_DSPR2
22 static void idct32_rows_dspr2(const int16_t *input, int16_t *output, 19 static void idct32_rows_dspr2(const int16_t *input, int16_t *output,
23 uint32_t no_rows) { 20 uint32_t no_rows) {
24 int16_t step1_0, step1_1, step1_2, step1_3, step1_4, step1_5, step1_6; 21 int16_t step1_0, step1_1, step1_2, step1_3, step1_4, step1_5, step1_6;
25 int16_t step1_7, step1_8, step1_9, step1_10, step1_11, step1_12, step1_13; 22 int16_t step1_7, step1_8, step1_9, step1_10, step1_11, step1_12, step1_13;
26 int16_t step1_14, step1_15, step1_16, step1_17, step1_18, step1_19, step1_20; 23 int16_t step1_14, step1_15, step1_16, step1_17, step1_18, step1_19, step1_20;
27 int16_t step1_21, step1_22, step1_23, step1_24, step1_25, step1_26, step1_27; 24 int16_t step1_21, step1_22, step1_23, step1_24, step1_25, step1_26, step1_27;
28 int16_t step1_28, step1_29, step1_30, step1_31; 25 int16_t step1_28, step1_29, step1_30, step1_31;
(...skipping 832 matching lines...) Expand 10 before | Expand all | Expand 10 after
861 output[28 * 32] = step1_3 - step2_28; 858 output[28 * 32] = step1_3 - step2_28;
862 output[29 * 32] = step1_2 - step2_29; 859 output[29 * 32] = step1_2 - step2_29;
863 output[30 * 32] = step1_1 - step2_30; 860 output[30 * 32] = step1_1 - step2_30;
864 output[31 * 32] = step1_0 - step2_31; 861 output[31 * 32] = step1_0 - step2_31;
865 862
866 input += 32; 863 input += 32;
867 output += 1; 864 output += 1;
868 } 865 }
869 } 866 }
870 867
871 void vp9_idct32x32_1024_add_dspr2(const int16_t *input, uint8_t *dest, 868 void vpx_idct32x32_1024_add_dspr2(const int16_t *input, uint8_t *dest,
872 int dest_stride) { 869 int dest_stride) {
873 DECLARE_ALIGNED(32, int16_t, out[32 * 32]); 870 DECLARE_ALIGNED(32, int16_t, out[32 * 32]);
874 int16_t *outptr = out; 871 int16_t *outptr = out;
875 uint32_t pos = 45; 872 uint32_t pos = 45;
876 873
877 /* bit positon for extract from acc */ 874 /* bit positon for extract from acc */
878 __asm__ __volatile__ ( 875 __asm__ __volatile__ (
879 "wrdsp %[pos], 1 \n\t" 876 "wrdsp %[pos], 1 \n\t"
880 : 877 :
881 : [pos] "r" (pos) 878 : [pos] "r" (pos)
882 ); 879 );
883 880
884 // Rows 881 // Rows
885 idct32_rows_dspr2(input, outptr, 32); 882 idct32_rows_dspr2(input, outptr, 32);
886 883
887 // Columns 884 // Columns
888 vp9_idct32_cols_add_blk_dspr2(out, dest, dest_stride); 885 vpx_idct32_cols_add_blk_dspr2(out, dest, dest_stride);
889 } 886 }
890 887
891 void vp9_idct32x32_34_add_dspr2(const int16_t *input, uint8_t *dest, 888 void vpx_idct32x32_34_add_dspr2(const int16_t *input, uint8_t *dest,
892 int stride) { 889 int stride) {
893 DECLARE_ALIGNED(32, int16_t, out[32 * 32]); 890 DECLARE_ALIGNED(32, int16_t, out[32 * 32]);
894 int16_t *outptr = out; 891 int16_t *outptr = out;
895 uint32_t i; 892 uint32_t i;
896 uint32_t pos = 45; 893 uint32_t pos = 45;
897 894
898 /* bit positon for extract from acc */ 895 /* bit positon for extract from acc */
899 __asm__ __volatile__ ( 896 __asm__ __volatile__ (
900 "wrdsp %[pos], 1 \n\t" 897 "wrdsp %[pos], 1 \n\t"
901 : 898 :
(...skipping 38 matching lines...) Expand 10 before | Expand all | Expand 10 after
940 "sw $zero, 36(%[outptr]) \n\t" 937 "sw $zero, 36(%[outptr]) \n\t"
941 "sw $zero, 40(%[outptr]) \n\t" 938 "sw $zero, 40(%[outptr]) \n\t"
942 "sw $zero, 44(%[outptr]) \n\t" 939 "sw $zero, 44(%[outptr]) \n\t"
943 940
944 : 941 :
945 : [outptr] "r" (outptr) 942 : [outptr] "r" (outptr)
946 ); 943 );
947 } 944 }
948 945
949 // Columns 946 // Columns
950 vp9_idct32_cols_add_blk_dspr2(out, dest, stride); 947 vpx_idct32_cols_add_blk_dspr2(out, dest, stride);
951 } 948 }
952 949
953 void vp9_idct32x32_1_add_dspr2(const int16_t *input, uint8_t *dest, 950 void vpx_idct32x32_1_add_dspr2(const int16_t *input, uint8_t *dest,
954 int stride) { 951 int stride) {
955 int r, out; 952 int r, out;
956 int32_t a1, absa1; 953 int32_t a1, absa1;
957 int32_t vector_a1; 954 int32_t vector_a1;
958 int32_t t1, t2, t3, t4; 955 int32_t t1, t2, t3, t4;
959 int32_t vector_1, vector_2, vector_3, vector_4; 956 int32_t vector_1, vector_2, vector_3, vector_4;
960 uint32_t pos = 45; 957 uint32_t pos = 45;
961 958
962 /* bit positon for extract from acc */ 959 /* bit positon for extract from acc */
963 __asm__ __volatile__ ( 960 __asm__ __volatile__ (
(...skipping 103 matching lines...) Expand 10 before | Expand all | Expand 10 after
1067 : [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3), [t4] "=&r" (t4), 1064 : [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3), [t4] "=&r" (t4),
1068 [vector_1] "=&r" (vector_1), [vector_2] "=&r" (vector_2), 1065 [vector_1] "=&r" (vector_1), [vector_2] "=&r" (vector_2),
1069 [vector_3] "=&r" (vector_3), [vector_4] "=&r" (vector_4), 1066 [vector_3] "=&r" (vector_3), [vector_4] "=&r" (vector_4),
1070 [dest] "+&r" (dest) 1067 [dest] "+&r" (dest)
1071 : [stride] "r" (stride), [vector_a1] "r" (vector_a1) 1068 : [stride] "r" (stride), [vector_a1] "r" (vector_a1)
1072 ); 1069 );
1073 } 1070 }
1074 } 1071 }
1075 } 1072 }
1076 #endif // #if HAVE_DSPR2 1073 #endif // #if HAVE_DSPR2
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