libvpx: Pull from upstream

source/libvpx/vpx_dsp/mips/idct16x16_msa.c

 /*
  *  Copyright (c) 2015 The WebM project authors. All Rights Reserved.
  *
  *  Use of this source code is governed by a BSD-style license
  *  that can be found in the LICENSE file in the root of the source
  *  tree. An additional intellectual property rights grant can be found
  *  in the file PATENTS.  All contributing project authors may
  *  be found in the AUTHORS file in the root of the source tree.
  */
 
 #include "vpx_dsp/mips/inv_txfm_msa.h"
 
-void vp9_idct16_1d_rows_msa(const int16_t *input, int16_t *output) {
+void vpx_idct16_1d_rows_msa(const int16_t *input, int16_t *output) {
   v8i16 loc0, loc1, loc2, loc3;
   v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14;
   v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15;
   v8i16 tmp5, tmp6, tmp7;
 
   LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
   input += 8;
   LD_SH8(input, 16, reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15);
 
   TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7,
@@ skipping 72 matching lines @@
   TRANSPOSE8x8_SH_SH(reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14,
                      reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14);
   ST_SH8(reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14, output, 16);
 
   /* transpose block */
   TRANSPOSE8x8_SH_SH(reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15,
                      reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15);
   ST_SH8(reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15, (output + 8), 16);
 }
 
-void vp9_idct16_1d_columns_addblk_msa(int16_t *input, uint8_t *dst,
+void vpx_idct16_1d_columns_addblk_msa(int16_t *input, uint8_t *dst,
                                       int32_t dst_stride) {
   v8i16 loc0, loc1, loc2, loc3;
   v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14;
   v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15;
   v8i16 tmp5, tmp6, tmp7;
 
   /* load up 8x8 */
   LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
   input += 8 * 16;
   /* load bottom 8x8 */
@@ skipping 77 matching lines @@
   SRARI_H4_SH(reg8, reg10, reg12, reg14, 6);
   VP9_ADDBLK_ST8x4_UB(dst, dst_stride, reg8, reg10, reg12, reg14);
   dst += (4 * dst_stride);
   SRARI_H4_SH(reg3, reg13, reg11, reg5, 6);
   VP9_ADDBLK_ST8x4_UB(dst, dst_stride, reg3, reg13, reg11, reg5);
   dst += (4 * dst_stride);
   SRARI_H4_SH(reg7, reg9, reg1, reg15, 6);
   VP9_ADDBLK_ST8x4_UB(dst, dst_stride, reg7, reg9, reg1, reg15);
 }
 
-void vp9_idct16x16_256_add_msa(const int16_t *input, uint8_t *dst,
+void vpx_idct16x16_256_add_msa(const int16_t *input, uint8_t *dst,
                                int32_t dst_stride) {
   int32_t i;
   DECLARE_ALIGNED(32, int16_t, out_arr[16 * 16]);
   int16_t *out = out_arr;
 
   /* transform rows */
   for (i = 0; i < 2; ++i) {
     /* process 16 * 8 block */
-    vp9_idct16_1d_rows_msa((input + (i << 7)), (out + (i << 7)));
+    vpx_idct16_1d_rows_msa((input + (i << 7)), (out + (i << 7)));
   }
 
   /* transform columns */
   for (i = 0; i < 2; ++i) {
     /* process 8 * 16 block */
-    vp9_idct16_1d_columns_addblk_msa((out + (i << 3)), (dst + (i << 3)),
+    vpx_idct16_1d_columns_addblk_msa((out + (i << 3)), (dst + (i << 3)),
                                      dst_stride);
   }
 }
 
-void vp9_idct16x16_10_add_msa(const int16_t *input, uint8_t *dst,
+void vpx_idct16x16_10_add_msa(const int16_t *input, uint8_t *dst,
                               int32_t dst_stride) {
   uint8_t i;
   DECLARE_ALIGNED(32, int16_t, out_arr[16 * 16]);
   int16_t *out = out_arr;
 
   /* process 16 * 8 block */
-  vp9_idct16_1d_rows_msa(input, out);
+  vpx_idct16_1d_rows_msa(input, out);
 
   /* short case just considers top 4 rows as valid output */
   out += 4 * 16;
   for (i = 12; i--;) {
     __asm__ __volatile__ (
         "sw     $zero,   0(%[out])     \n\t"
         "sw     $zero,   4(%[out])     \n\t"
         "sw     $zero,   8(%[out])     \n\t"
         "sw     $zero,  12(%[out])     \n\t"
         "sw     $zero,  16(%[out])     \n\t"
         "sw     $zero,  20(%[out])     \n\t"
         "sw     $zero,  24(%[out])     \n\t"
         "sw     $zero,  28(%[out])     \n\t"
 
         :
         : [out] "r" (out)
     );
 
     out += 16;
   }
 
   out = out_arr;
 
   /* transform columns */
   for (i = 0; i < 2; ++i) {
     /* process 8 * 16 block */
-    vp9_idct16_1d_columns_addblk_msa((out + (i << 3)), (dst + (i << 3)),
+    vpx_idct16_1d_columns_addblk_msa((out + (i << 3)), (dst + (i << 3)),
                                      dst_stride);
   }
 }
 
-void vp9_idct16x16_1_add_msa(const int16_t *input, uint8_t *dst,
+void vpx_idct16x16_1_add_msa(const int16_t *input, uint8_t *dst,
                              int32_t dst_stride) {
   uint8_t i;
   int16_t out;
   v8i16 vec, res0, res1, res2, res3, res4, res5, res6, res7;
   v16u8 dst0, dst1, dst2, dst3, tmp0, tmp1, tmp2, tmp3;
 
   out = ROUND_POWER_OF_TWO((input[0] * cospi_16_64), DCT_CONST_BITS);
   out = ROUND_POWER_OF_TWO((out * cospi_16_64), DCT_CONST_BITS);
   out = ROUND_POWER_OF_TWO(out, 6);
 
   vec = __msa_fill_h(out);
 
   for (i = 4; i--;) {
     LD_UB4(dst, dst_stride, dst0, dst1, dst2, dst3);
     UNPCK_UB_SH(dst0, res0, res4);
     UNPCK_UB_SH(dst1, res1, res5);
     UNPCK_UB_SH(dst2, res2, res6);
     UNPCK_UB_SH(dst3, res3, res7);
     ADD4(res0, vec, res1, vec, res2, vec, res3, vec, res0, res1, res2, res3);
     ADD4(res4, vec, res5, vec, res6, vec, res7, vec, res4, res5, res6, res7);
     CLIP_SH4_0_255(res0, res1, res2, res3);
     CLIP_SH4_0_255(res4, res5, res6, res7);
     PCKEV_B4_UB(res4, res0, res5, res1, res6, res2, res7, res3,
                 tmp0, tmp1, tmp2, tmp3);
     ST_UB4(tmp0, tmp1, tmp2, tmp3, dst, dst_stride);
     dst += (4 * dst_stride);
   }
 }
 
-void vp9_iadst16_1d_rows_msa(const int16_t *input, int16_t *output) {
+void vpx_iadst16_1d_rows_msa(const int16_t *input, int16_t *output) {
   v8i16 r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15;
   v8i16 l0, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15;
 
   /* load input data */
   LD_SH16(input, 8,
           l0, l8, l1, l9, l2, l10, l3, l11, l4, l12, l5, l13, l6, l14, l7, l15);
   TRANSPOSE8x8_SH_SH(l0, l1, l2, l3, l4, l5, l6, l7,
                      l0, l1, l2, l3, l4, l5, l6, l7);
   TRANSPOSE8x8_SH_SH(l8, l9, l10, l11, l12, l13, l14, l15,
                      l8, l9, l10, l11, l12, l13, l14, l15);
@@ skipping 10 matching lines @@
   l15 = -r1;
 
   TRANSPOSE8x8_SH_SH(r0, l1, r12, l3, r6, r14, r10, r2,
                      l0, l1, l2, l3, l4, l5, l6, l7);
   ST_SH8(l0, l1, l2, l3, l4, l5, l6, l7, output, 16);
   TRANSPOSE8x8_SH_SH(r3, r11, r15, r7, r5, l13, r9, l15,
                      l8, l9, l10, l11, l12, l13, l14, l15);
   ST_SH8(l8, l9, l10, l11, l12, l13, l14, l15, (output + 8), 16);
 }
 
-void vp9_iadst16_1d_columns_addblk_msa(int16_t *input, uint8_t *dst,
+void vpx_iadst16_1d_columns_addblk_msa(int16_t *input, uint8_t *dst,
                                        int32_t dst_stride) {
   v8i16 v0, v2, v4, v6, k0, k1, k2, k3;
   v8i16 r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15;
   v8i16 out0, out1, out2, out3, out4, out5, out6, out7;
   v8i16 out8, out9, out10, out11, out12, out13, out14, out15;
   v8i16 g0, g1, g2, g3, g4, g5, g6, g7, g8, g9, g10, g11, g12, g13, g14, g15;
   v8i16 h0, h1, h2, h3, h4, h5, h6, h7, h8, h9, h10, h11;
   v8i16 res0, res1, res2, res3, res4, res5, res6, res7;
   v8i16 res8, res9, res10, res11, res12, res13, res14, res15;
   v16u8 dst0, dst1, dst2, dst3, dst4, dst5, dst6, dst7;
@@ skipping 143 matching lines @@
   SRARI_H2_SH(out14, out15, 6);
   dst14 = LD_UB(dst + 5 * dst_stride);
   dst15 = LD_UB(dst + 10 * dst_stride);
   ILVR_B2_SH(zero, dst14, zero, dst15, res14, res15);
   ADD2(res14, out14, res15, out15, res14, res15);
   CLIP_SH2_0_255(res14, res15);
   PCKEV_B2_SH(res14, res14, res15, res15, res14, res15);
   ST8x1_UB(res14, dst + 5 * dst_stride);
   ST8x1_UB(res15, dst + 10 * dst_stride);
 }