VM: Clean up and fix bugs in instructions patterns

runtime/vm/instructions_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM64.
 #if defined(TARGET_ARCH_ARM64)
 
 #include "vm/assembler.h"
 #include "vm/constants_arm64.h"
 #include "vm/cpu.h"
@@ skipping 190 matching lines @@
 
       start -= Instr::kInstrSize;
       instr = Instr::At(start);
       ASSERT(instr->IsMoveWideOp());
       ASSERT(instr->RdField() == *reg);
       ASSERT(instr->Bits(29, 2) == 2);  // movz dst, low_offset, 0
       ASSERT(instr->HWField() == 0);
       offset |= instr->Imm16Field();
     }
   }
+  // PP is untagged on ARM64.
   ASSERT(Utils::IsAligned(offset, 8));
-  *index = (offset - Array::data_offset()) / 8;
+  *index = ObjectPool::IndexFromOffset(offset - kHeapObjectTag);
   return start;
 }
 
 
 // Encodes a load sequence ending at 'end'. Encodes a fixed length two
 // instruction load from the pool pointer in PP using the destination
 // register reg as a temporary for the base address.
 // Assumes that the location has already been validated for patching.
 void InstructionPattern::EncodeLoadWordFromPoolFixed(uword end,
                                                      int32_t offset) {
@@ skipping 143 matching lines @@
 bool ReturnPattern::IsValid() const {
   Instr* bx_lr = Instr::At(pc_);
   const Register crn = ConcreteRegister(LR);
   const int32_t instruction = RET | (static_cast<int32_t>(crn) << kRnShift);
   return bx_lr->InstructionBits() == instruction;
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM64