Use separate random number generator for each randomization pass

src/IceTargetLoweringX8664Traits.h

 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 357 matching lines @@
     REGX8664_TABLE
 
 #undef X
 
     return Registers;
   }
 
   static void
   makeRandomRegisterPermutation(GlobalContext *Ctx, Cfg *Func,
                                 llvm::SmallVectorImpl<int32_t> &Permutation,
-                                const llvm::SmallBitVector &ExcludeRegisters) {
+                                const llvm::SmallBitVector &ExcludeRegisters,
+                                uint64_t Salt) {
     // TODO(stichnot): Declaring Permutation this way loses type/size
     // information.  Fix this in conjunction with the caller-side TODO.
     assert(Permutation.size() >= RegisterSet::Reg_NUM);
     // Expected upper bound on the number of registers in a single equivalence
     // class.  For x86-64, this would comprise the 16 XMM registers.  This is
     // for performance, not correctness.
     static const unsigned MaxEquivalenceClassSize = 8;
     typedef llvm::SmallVector<int32_t, MaxEquivalenceClassSize> RegisterList;
     typedef std::map<uint32_t, RegisterList> EquivalenceClassMap;
     EquivalenceClassMap EquivalenceClasses;
@@ skipping 10 matching lines @@
     ++NumPreserved;                                                            \
   } else {                                                                     \
     const uint32_t Index = (scratch << 0) | (preserved << 1) |                 \
                            (/*isI8=*/1 << 2) | (isInt << 3) | (isFP << 4);     \
     /* val is assigned to an equivalence class based on its properties. */     \
     EquivalenceClasses[Index].push_back(RegisterSet::val);                     \
   }
     REGX8664_TABLE
 #undef X
 
-    RandomNumberGeneratorWrapper RNG(Ctx->getRNG());
+    // Create a random number generator for regalloc randomization.
+    RandomNumberGenerator RNG(Ctx->getFlags().getRandomSeed(),
+                              RPE_RegAllocRandomization, Salt);
+    RandomNumberGeneratorWrapper RNGW(RNG);
 
     // Shuffle the resulting equivalence classes.
     for (auto I : EquivalenceClasses) {
       const RegisterList &List = I.second;
       RegisterList Shuffled(List);
-      RandomShuffle(Shuffled.begin(), Shuffled.end(), RNG);
+      RandomShuffle(Shuffled.begin(), Shuffled.end(), RNGW);
       for (size_t SI = 0, SE = Shuffled.size(); SI < SE; ++SI) {
         Permutation[List[SI]] = Shuffled[SI];
         ++NumShuffled;
       }
     }
 
     assert(NumShuffled + NumPreserved == RegisterSet::Reg_NUM);
 
     if (Func->isVerbose(IceV_Random)) {
       OstreamLocker L(Func->getContext());
@@ skipping 292 matching lines @@
 
 } // end of namespace X86Internal
 
 namespace X8664 {
 using Traits = ::Ice::X86Internal::MachineTraits<TargetX8664>;
 } // end of namespace X8664
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H