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Side by Side Diff: src/IceTargetLoweringX86Base.h

Issue 1300993002: Use separate random number generator for each randomization pass (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 4 months ago
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1 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===// 1 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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173 void lowerPhi(const InstPhi *Inst) override; 173 void lowerPhi(const InstPhi *Inst) override;
174 void lowerSelect(const InstSelect *Inst) override; 174 void lowerSelect(const InstSelect *Inst) override;
175 void lowerStore(const InstStore *Inst) override; 175 void lowerStore(const InstStore *Inst) override;
176 void lowerSwitch(const InstSwitch *Inst) override; 176 void lowerSwitch(const InstSwitch *Inst) override;
177 void lowerUnreachable(const InstUnreachable *Inst) override; 177 void lowerUnreachable(const InstUnreachable *Inst) override;
178 void lowerOther(const Inst *Instr) override; 178 void lowerOther(const Inst *Instr) override;
179 void lowerRMW(const typename Traits::Insts::FakeRMW *RMW); 179 void lowerRMW(const typename Traits::Insts::FakeRMW *RMW);
180 void prelowerPhis() override; 180 void prelowerPhis() override;
181 void doAddressOptLoad() override; 181 void doAddressOptLoad() override;
182 void doAddressOptStore() override; 182 void doAddressOptStore() override;
183 void randomlyInsertNop(float Probability) override; 183 void randomlyInsertNop(float Probability,
184 RandomNumberGenerator &RNG) override;
184 185
185 /// Naive lowering of cmpxchg. 186 /// Naive lowering of cmpxchg.
186 void lowerAtomicCmpxchg(Variable *DestPrev, Operand *Ptr, Operand *Expected, 187 void lowerAtomicCmpxchg(Variable *DestPrev, Operand *Ptr, Operand *Expected,
187 Operand *Desired); 188 Operand *Desired);
188 /// Attempt a more optimized lowering of cmpxchg. Returns true if optimized. 189 /// Attempt a more optimized lowering of cmpxchg. Returns true if optimized.
189 bool tryOptimizedCmpxchgCmpBr(Variable *DestPrev, Operand *Ptr, 190 bool tryOptimizedCmpxchgCmpBr(Variable *DestPrev, Operand *Ptr,
190 Operand *Expected, Operand *Desired); 191 Operand *Expected, Operand *Desired);
191 void lowerAtomicRMW(Variable *Dest, uint32_t Operation, Operand *Ptr, 192 void lowerAtomicRMW(Variable *Dest, uint32_t Operation, Operand *Ptr,
192 Operand *Val); 193 Operand *Val);
193 void lowerCountZeros(bool Cttz, Type Ty, Variable *Dest, Operand *FirstVal, 194 void lowerCountZeros(bool Cttz, Type Ty, Variable *Dest, Operand *FirstVal,
(...skipping 68 matching lines...) Expand 10 before | Expand all | Expand 10 after
262 Variable *makeVectorOfHighOrderBits(Type Ty, 263 Variable *makeVectorOfHighOrderBits(Type Ty,
263 int32_t RegNum = Variable::NoRegister); 264 int32_t RegNum = Variable::NoRegister);
264 Variable *makeVectorOfFabsMask(Type Ty, 265 Variable *makeVectorOfFabsMask(Type Ty,
265 int32_t RegNum = Variable::NoRegister); 266 int32_t RegNum = Variable::NoRegister);
266 /// @} 267 /// @}
267 268
268 /// Return a memory operand corresponding to a stack allocated Variable. 269 /// Return a memory operand corresponding to a stack allocated Variable.
269 typename Traits::X86OperandMem * 270 typename Traits::X86OperandMem *
270 getMemoryOperandForStackSlot(Type Ty, Variable *Slot, uint32_t Offset = 0); 271 getMemoryOperandForStackSlot(Type Ty, Variable *Slot, uint32_t Offset = 0);
271 272
272 void makeRandomRegisterPermutation( 273 void
273 llvm::SmallVectorImpl<int32_t> &Permutation, 274 makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation,
274 const llvm::SmallBitVector &ExcludeRegisters) const override; 275 const llvm::SmallBitVector &ExcludeRegisters,
276 uint64_t Salt) const override;
275 277
276 /// The following are helpers that insert lowered x86 instructions 278 /// The following are helpers that insert lowered x86 instructions
277 /// with minimal syntactic overhead, so that the lowering code can 279 /// with minimal syntactic overhead, so that the lowering code can
278 /// look as close to assembly as practical. 280 /// look as close to assembly as practical.
279 void _adc(Variable *Dest, Operand *Src0) { 281 void _adc(Variable *Dest, Operand *Src0) {
280 Context.insert(Traits::Insts::Adc::create(Func, Dest, Src0)); 282 Context.insert(Traits::Insts::Adc::create(Func, Dest, Src0));
281 } 283 }
282 void _adc_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) { 284 void _adc_rmw(typename Traits::X86OperandMem *DestSrc0, Operand *Src1) {
283 Context.insert(Traits::Insts::AdcRMW::create(Func, DestSrc0, Src1)); 285 Context.insert(Traits::Insts::AdcRMW::create(Func, DestSrc0, Src1));
284 } 286 }
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694 } 696 }
695 697
696 BoolFolding FoldingInfo; 698 BoolFolding FoldingInfo;
697 }; 699 };
698 } // end of namespace X86Internal 700 } // end of namespace X86Internal
699 } // end of namespace Ice 701 } // end of namespace Ice
700 702
701 #include "IceTargetLoweringX86BaseImpl.h" 703 #include "IceTargetLoweringX86BaseImpl.h"
702 704
703 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H 705 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H
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