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| 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 109 void lowerLoad(const InstLoad *Inst) override; | 109 void lowerLoad(const InstLoad *Inst) override; |
| 110 void lowerPhi(const InstPhi *Inst) override; | 110 void lowerPhi(const InstPhi *Inst) override; |
| 111 void lowerRet(const InstRet *Inst) override; | 111 void lowerRet(const InstRet *Inst) override; |
| 112 void lowerSelect(const InstSelect *Inst) override; | 112 void lowerSelect(const InstSelect *Inst) override; |
| 113 void lowerStore(const InstStore *Inst) override; | 113 void lowerStore(const InstStore *Inst) override; |
| 114 void lowerSwitch(const InstSwitch *Inst) override; | 114 void lowerSwitch(const InstSwitch *Inst) override; |
| 115 void lowerUnreachable(const InstUnreachable *Inst) override; | 115 void lowerUnreachable(const InstUnreachable *Inst) override; |
| 116 void prelowerPhis() override; | 116 void prelowerPhis() override; |
| 117 void doAddressOptLoad() override; | 117 void doAddressOptLoad() override; |
| 118 void doAddressOptStore() override; | 118 void doAddressOptStore() override; |
| 119 void randomlyInsertNop(float Probability) override; | 119 void randomlyInsertNop(float Probability, |
| 120 void makeRandomRegisterPermutation( | 120 RandomNumberGenerator &RNG) override; |
| 121 llvm::SmallVectorImpl<int32_t> &Permutation, | 121 void |
| 122 const llvm::SmallBitVector &ExcludeRegisters) const override; | 122 makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation, |
| 123 const llvm::SmallBitVector &ExcludeRegisters, |
| 124 uint64_t Salt) const override; |
| 123 | 125 |
| 124 static Type stackSlotType(); | 126 static Type stackSlotType(); |
| 125 | 127 |
| 126 bool UsesFramePointer = false; | 128 bool UsesFramePointer = false; |
| 127 bool NeedsStackAlignment = false; | 129 bool NeedsStackAlignment = false; |
| 128 llvm::SmallBitVector TypeToRegisterSet[IceType_NUM]; | 130 llvm::SmallBitVector TypeToRegisterSet[IceType_NUM]; |
| 129 llvm::SmallBitVector ScratchRegs; | 131 llvm::SmallBitVector ScratchRegs; |
| 130 llvm::SmallBitVector RegsUsed; | 132 llvm::SmallBitVector RegsUsed; |
| 131 VarList PhysicalRegisters[IceType_NUM]; | 133 VarList PhysicalRegisters[IceType_NUM]; |
| 132 | 134 |
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| 170 protected: | 172 protected: |
| 171 explicit TargetHeaderMIPS32(GlobalContext *Ctx); | 173 explicit TargetHeaderMIPS32(GlobalContext *Ctx); |
| 172 | 174 |
| 173 private: | 175 private: |
| 174 ~TargetHeaderMIPS32() = default; | 176 ~TargetHeaderMIPS32() = default; |
| 175 }; | 177 }; |
| 176 | 178 |
| 177 } // end of namespace Ice | 179 } // end of namespace Ice |
| 178 | 180 |
| 179 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H | 181 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H |
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