Use separate random number generator for each randomization pass

src/IceTargetLowering.h

 //===- subzero/src/IceTargetLowering.h - Lowering interface -----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 135 matching lines @@
   virtual void translateO1() {
     Func->setError("Target doesn't specify O1 lowering steps.");
   }
   virtual void translateO2() {
     Func->setError("Target doesn't specify O2 lowering steps.");
   }
 
   /// Tries to do address mode optimization on a single instruction.
   void doAddressOpt();
   /// Randomly insert NOPs.
-  void doNopInsertion();
+  void doNopInsertion(RandomNumberGenerator &RNG);
   /// Lowers a single non-Phi instruction.
   void lower();
   /// Inserts and lowers a single high-level instruction at a specific insertion
   /// point.
   void lowerInst(CfgNode *Node, InstList::iterator Next, InstHighLevel *Instr);
   /// Does preliminary lowering of the set of Phi instructions in the
   /// current node.  The main intention is to do what's needed to keep
   /// the unlowered Phi instructions consistent with the lowered
   /// non-Phi instructions, e.g. to lower 64-bit operands on a 32-bit
   /// target.
@@ skipping 39 matching lines @@
     RegSet_FramePointer = 1 << 3,
     RegSet_All = ~RegSet_None
   };
   typedef uint32_t RegSetMask;
 
   virtual llvm::SmallBitVector getRegisterSet(RegSetMask Include,
                                               RegSetMask Exclude) const = 0;
   virtual const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const = 0;
   void regAlloc(RegAllocKind Kind);
 
-  virtual void makeRandomRegisterPermutation(
-      llvm::SmallVectorImpl<int32_t> &Permutation,
-      const llvm::SmallBitVector &ExcludeRegisters) const = 0;
+  virtual void
+  makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation,
+                                const llvm::SmallBitVector &ExcludeRegisters,
+                                uint64_t Salt) const = 0;
 
   /// Save/restore any mutable state for the situation where code
   /// emission needs multiple passes, such as sandboxing or relaxation.
   /// Subclasses may provide their own implementation, but should be
   /// sure to also call the parent class's methods.
   virtual void snapshotEmitState() {
     SnapshotStackAdjustment = StackAdjustment;
   }
   virtual void rollbackEmitState() {
     StackAdjustment = SnapshotStackAdjustment;
@@ skipping 43 matching lines @@
   virtual void lowerPhi(const InstPhi *Inst) = 0;
   virtual void lowerRet(const InstRet *Inst) = 0;
   virtual void lowerSelect(const InstSelect *Inst) = 0;
   virtual void lowerStore(const InstStore *Inst) = 0;
   virtual void lowerSwitch(const InstSwitch *Inst) = 0;
   virtual void lowerUnreachable(const InstUnreachable *Inst) = 0;
   virtual void lowerOther(const Inst *Instr);
 
   virtual void doAddressOptLoad() {}
   virtual void doAddressOptStore() {}
-  virtual void randomlyInsertNop(float Probability) = 0;
+  virtual void randomlyInsertNop(float Probability,
+                                 RandomNumberGenerator &RNG) = 0;
   /// This gives the target an opportunity to post-process the lowered
   /// expansion before returning.
   virtual void postLower() {}
 
   /// Find two-address non-SSA instructions and set the DestNonKillable flag
   /// to keep liveness analysis consistent.
   void inferTwoAddress();
 
   /// Make a pass over the Cfg to determine which variables need stack slots
   /// and place them in a sorted list (SortedSpilledVariables). Among those,
@@ skipping 157 matching lines @@
   virtual void lower() {}
 
 protected:
   explicit TargetHeaderLowering(GlobalContext *Ctx) : Ctx(Ctx) {}
   GlobalContext *Ctx;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERING_H