MIPS:[turbofan] Improve boolean materialization compares.

src/compiler/mips64/code-generator-mips64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/code-generator.h"
 #include "src/compiler/code-generator-impl.h"
 #include "src/compiler/gap-resolver.h"
 #include "src/compiler/node-matchers.h"
 #include "src/mips/macro-assembler-mips.h"
 #include "src/scopes.h"
@@ skipping 182 matching lines @@
 };
 
 
 class OutOfLineCeil final : public OutOfLineRound {
  public:
   OutOfLineCeil(CodeGenerator* gen, DoubleRegister result)
       : OutOfLineRound(gen, result) {}
 };
 
 
-Condition FlagsConditionToConditionCmp(FlagsCondition condition) {
+Condition FlagsConditionToConditionCmp(bool& predicate,
+                                       FlagsCondition condition) {
   switch (condition) {
     case kEqual:
+      predicate = true;
       return eq;
     case kNotEqual:
+      predicate = false;
       return ne;
     case kSignedLessThan:
+      predicate = true;
       return lt;
     case kSignedGreaterThanOrEqual:
+      predicate = false;
       return ge;
     case kSignedLessThanOrEqual:
+      predicate = false;
       return le;
     case kSignedGreaterThan:
+      predicate = true;
       return gt;
     case kUnsignedLessThan:
+      predicate = true;
       return lo;
     case kUnsignedGreaterThanOrEqual:
+      predicate = false;
       return hs;
     case kUnsignedLessThanOrEqual:
+      predicate = false;
       return ls;
     case kUnsignedGreaterThan:
+      predicate = true;
       return hi;
     case kUnorderedEqual:
     case kUnorderedNotEqual:
+      predicate = true;
       break;
     default:
+      predicate = true;
       break;
   }
   UNREACHABLE();
   return kNoCondition;
 }
 
 
-Condition FlagsConditionToConditionTst(FlagsCondition condition) {
+Condition FlagsConditionToConditionTst(bool& predicate,
+                                       FlagsCondition condition) {
   switch (condition) {
     case kNotEqual:
+      predicate = false;
       return ne;
     case kEqual:
+      predicate = true;
       return eq;
     default:
+      predicate = true;
       break;
   }
   UNREACHABLE();
   return kNoCondition;
 }
 
 
-Condition FlagsConditionToConditionOvf(FlagsCondition condition) {
+Condition FlagsConditionToConditionOvf(bool& predicate,
+                                       FlagsCondition condition) {
   switch (condition) {
     case kOverflow:
+      predicate = true;
       return ne;
     case kNotOverflow:
+      predicate = false;
       return eq;
     default:
+      predicate = true;
       break;
   }
   UNREACHABLE();
   return kNoCondition;
 }
 
 
 FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
                                              FlagsCondition condition) {
   switch (condition) {
@@ skipping 691 matching lines @@
   return false;
 }
 
 
 // Assembles branches after an instruction.
 void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
   MipsOperandConverter i(this, instr);
   Label* tlabel = branch->true_label;
   Label* flabel = branch->false_label;
   Condition cc = kNoCondition;
-
+  bool predicate;
   // MIPS does not have condition code flags, so compare and branch are
   // implemented differently than on the other arch's. The compare operations
   // emit mips psuedo-instructions, which are handled here by branch
   // instructions that do the actual comparison. Essential that the input
   // registers to compare pseudo-op are not modified before this branch op, as
   // they are tested here.
 
   if (instr->arch_opcode() == kMips64Tst) {
-    cc = FlagsConditionToConditionTst(branch->condition);
+    cc = FlagsConditionToConditionTst(predicate, branch->condition);
     __ And(at, i.InputRegister(0), i.InputOperand(1));
     __ Branch(tlabel, cc, at, Operand(zero_reg));
   } else if (instr->arch_opcode() == kMips64Dadd ||
              instr->arch_opcode() == kMips64Dsub) {
-    cc = FlagsConditionToConditionOvf(branch->condition);
+    cc = FlagsConditionToConditionOvf(predicate, branch->condition);
     __ dsra32(kScratchReg, i.OutputRegister(), 0);
     __ sra(at, i.OutputRegister(), 31);
     __ Branch(tlabel, cc, at, Operand(kScratchReg));
   } else if (instr->arch_opcode() == kMips64Cmp) {
-    cc = FlagsConditionToConditionCmp(branch->condition);
+    cc = FlagsConditionToConditionCmp(predicate, branch->condition);
     __ Branch(tlabel, cc, i.InputRegister(0), i.InputOperand(1));
   } else if (instr->arch_opcode() == kMips64CmpS) {
     if (!convertCondition(branch->condition, cc)) {
       UNSUPPORTED_COND(kMips64CmpS, branch->condition);
     }
     __ BranchF32(tlabel, NULL, cc, i.InputSingleRegister(0),
                  i.InputSingleRegister(1));
   } else if (instr->arch_opcode() == kMips64CmpD) {
     if (!convertCondition(branch->condition, cc)) {
       UNSUPPORTED_COND(kMips64CmpD, branch->condition);
@@ skipping 19 matching lines @@
                                         FlagsCondition condition) {
   MipsOperandConverter i(this, instr);
   Label done;
 
   // Materialize a full 32-bit 1 or 0 value. The result register is always the
   // last output of the instruction.
   Label false_value;
   DCHECK_NE(0u, instr->OutputCount());
   Register result = i.OutputRegister(instr->OutputCount() - 1);
   Condition cc = kNoCondition;
-
+  bool predicate;
   // MIPS does not have condition code flags, so compare and branch are
   // implemented differently than on the other arch's. The compare operations
   // emit mips pseudo-instructions, which are checked and handled here.
 
-  // For materializations, we use delay slot to set the result true, and
-  // in the false case, where we fall through the branch, we reset the result
-  // false.
-
   if (instr->arch_opcode() == kMips64Tst) {
-    cc = FlagsConditionToConditionTst(condition);
-    __ And(at, i.InputRegister(0), i.InputOperand(1));
-    __ Branch(USE_DELAY_SLOT, &done, cc, at, Operand(zero_reg));
-    __ li(result, Operand(1));  // In delay slot.
+    cc = FlagsConditionToConditionTst(predicate, condition);
+    __ And(kScratchReg, i.InputRegister(0), i.InputOperand(1));
+    __ xori(kScratchReg2, zero_reg, 1);  // Create 1 for true.
+    if (kArchVariant != kMips64r6) {
+      if (predicate) {
+        __ Movn(result, zero_reg, kScratchReg);
+        __ Movz(result, kScratchReg2, kScratchReg);
+      } else {
+        __ Movz(result, zero_reg, kScratchReg);
+        __ Movn(result, kScratchReg2, kScratchReg);
+      }
+    } else {
+      if (predicate) {
+        __ seleqz(result, kScratchReg2, kScratchReg);
+      } else {
+        __ selnez(result, kScratchReg2, kScratchReg);
+      }
+    }
+    return;
   } else if (instr->arch_opcode() == kMips64Dadd ||
              instr->arch_opcode() == kMips64Dsub) {
-    cc = FlagsConditionToConditionOvf(condition);
-    __ dsra32(kScratchReg, i.OutputRegister(), 0);
-    __ sra(at, i.OutputRegister(), 31);
-    __ Branch(USE_DELAY_SLOT, &done, cc, at, Operand(kScratchReg));
-    __ li(result, Operand(1));  // In delay slot.
+    FlagsConditionToConditionOvf(predicate, condition);
+    // Check for overflow creates 1 or 0 for result.
+    __ dsrl32(kScratchReg, i.OutputRegister(), 31);
+    __ srl(at, i.OutputRegister(), 31);
+    __ xor_(result, kScratchReg, at);
+    if (!predicate)  // Toggle result for not overflow.
+      __ xori(result, result, 1);
+    return;
   } else if (instr->arch_opcode() == kMips64Cmp) {
-    Register left = i.InputRegister(0);
-    Operand right = i.InputOperand(1);
-    cc = FlagsConditionToConditionCmp(condition);
-    __ Branch(USE_DELAY_SLOT, &done, cc, left, right);
-    __ li(result, Operand(1));  // In delay slot.
+    cc = FlagsConditionToConditionCmp(predicate, condition);
+    switch (cc) {
+      case eq:
+      case ne: {
+        Register left = i.InputRegister(0);
+        Operand right = i.InputOperand(1);
+        __ Dsubu(kScratchReg, left, right);
+        __ xori(kScratchReg2, zero_reg, 1);
+        if (kArchVariant != kMips64r6) {
+          if (predicate) {
+            __ Movn(result, zero_reg, kScratchReg);
+            __ Movz(result, kScratchReg2, kScratchReg);
+          } else {
+            __ Movz(result, zero_reg, kScratchReg);
+            __ Movn(result, kScratchReg2, kScratchReg);
+          }
+        } else {
+          if (predicate) {
+            __ seleqz(result, kScratchReg2, kScratchReg);
+          } else {
+            __ selnez(result, kScratchReg2, kScratchReg);
+          }
+        }
+      } break;
+      case lt:
+      case ge: {
+        Register left = i.InputRegister(0);
+        Operand right = i.InputOperand(1);
+        __ Slt(result, left, right);
+        if (!predicate) {
+          __ xori(result, result, 1);
+        }
+      } break;
+      case gt:
+      case le: {
+        Register left = i.InputRegister(1);
+        Operand right = i.InputOperand(0);
+        __ Slt(result, left, right);
+        if (!predicate) {
+          __ xori(result, result, 1);
+        }
+      } break;
+      case lo:
+      case hs: {
+        Register left = i.InputRegister(0);
+        Operand right = i.InputOperand(1);
+        __ Sltu(result, left, right);
+        if (!predicate) {
+          __ xori(result, result, 1);
+        }
+      } break;
+      case hi:
+      case ls: {
+        Register left = i.InputRegister(1);
+        Operand right = i.InputOperand(0);
+        __ Sltu(result, left, right);
+        if (!predicate) {
+          __ xori(result, result, 1);
+        }
+      } break;
+      default:
+        UNREACHABLE();
+    }
+    return;
   } else if (instr->arch_opcode() == kMips64CmpD ||
              instr->arch_opcode() == kMips64CmpS) {
     FPURegister left = i.InputDoubleRegister(0);
     FPURegister right = i.InputDoubleRegister(1);
 
-    bool predicate;
     FPUCondition cc = FlagsConditionToConditionCmpFPU(predicate, condition);
     if (kArchVariant != kMips64r6) {
       __ li(result, Operand(1));
       if (instr->arch_opcode() == kMips64CmpD) {
         __ c(cc, D, left, right);
       } else {
         DCHECK(instr->arch_opcode() == kMips64CmpS);
         __ c(cc, S, left, right);
       }
       if (predicate) {
@@ skipping 13 matching lines @@
       if (!predicate)             // Toggle result for not equal.
         __ xori(result, result, 1);
     }
     return;
   } else {
     PrintF("AssembleArchBranch Unimplemented arch_opcode is : %d\n",
            instr->arch_opcode());
     TRACE_UNIMPL();
     UNIMPLEMENTED();
   }
-  // Fallthru case is the false materialization.
-  __ bind(&false_value);
-  __ li(result, Operand(static_cast<int64_t>(0)));
-  __ bind(&done);
 }
 
 
 void CodeGenerator::AssembleArchLookupSwitch(Instruction* instr) {
   MipsOperandConverter i(this, instr);
   Register input = i.InputRegister(0);
   for (size_t index = 2; index < instr->InputCount(); index += 2) {
     __ li(at, Operand(i.InputInt32(index + 0)));
     __ beq(input, at, GetLabel(i.InputRpo(index + 1)));
   }
@@ skipping 336 matching lines @@
       }
     }
   }
 }
 
 #undef __
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8