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Issue 12939010: MIPS: Critical fix for label binding in RegExp engine when trampoline is emitted. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 7 years, 9 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 1090 matching lines...) Expand 10 before | Expand all | Expand 10 after
1101 bind(&done); 1101 bind(&done);
1102 } 1102 }
1103 1103
1104 1104
1105 void MacroAssembler::BranchF(Label* target, 1105 void MacroAssembler::BranchF(Label* target,
1106 Label* nan, 1106 Label* nan,
1107 Condition cc, 1107 Condition cc,
1108 FPURegister cmp1, 1108 FPURegister cmp1,
1109 FPURegister cmp2, 1109 FPURegister cmp2,
1110 BranchDelaySlot bd) { 1110 BranchDelaySlot bd) {
1111 BlockTrampolinePoolScope block_trampoline_pool(this);
1111 if (cc == al) { 1112 if (cc == al) {
1112 Branch(bd, target); 1113 Branch(bd, target);
1113 return; 1114 return;
1114 } 1115 }
1115 1116
1116 ASSERT(nan || target); 1117 ASSERT(nan || target);
1117 // Check for unordered (NaN) cases. 1118 // Check for unordered (NaN) cases.
1118 if (nan) { 1119 if (nan) {
1119 c(UN, D, cmp1, cmp2); 1120 c(UN, D, cmp1, cmp2);
1120 bc1t(nan); 1121 bc1t(nan);
(...skipping 572 matching lines...) Expand 10 before | Expand all | Expand 10 after
1693 const Operand& rt, 1694 const Operand& rt,
1694 BranchDelaySlot bdslot) { 1695 BranchDelaySlot bdslot) {
1695 BRANCH_ARGS_CHECK(cond, rs, rt); 1696 BRANCH_ARGS_CHECK(cond, rs, rt);
1696 ASSERT(!rs.is(zero_reg)); 1697 ASSERT(!rs.is(zero_reg));
1697 Register r2 = no_reg; 1698 Register r2 = no_reg;
1698 Register scratch = at; 1699 Register scratch = at;
1699 1700
1700 if (rt.is_reg()) { 1701 if (rt.is_reg()) {
1701 // NOTE: 'at' can be clobbered by Branch but it is legal to use it as rs or 1702 // NOTE: 'at' can be clobbered by Branch but it is legal to use it as rs or
1702 // rt. 1703 // rt.
1704 BlockTrampolinePoolScope block_trampoline_pool(this);
1703 r2 = rt.rm_; 1705 r2 = rt.rm_;
1704 switch (cond) { 1706 switch (cond) {
1705 case cc_always: 1707 case cc_always:
1706 b(offset); 1708 b(offset);
1707 break; 1709 break;
1708 case eq: 1710 case eq:
1709 beq(rs, r2, offset); 1711 beq(rs, r2, offset);
1710 break; 1712 break;
1711 case ne: 1713 case ne:
1712 bne(rs, r2, offset); 1714 bne(rs, r2, offset);
(...skipping 65 matching lines...) Expand 10 before | Expand all | Expand 10 after
1778 beq(scratch, zero_reg, offset); 1780 beq(scratch, zero_reg, offset);
1779 } 1781 }
1780 break; 1782 break;
1781 default: 1783 default:
1782 UNREACHABLE(); 1784 UNREACHABLE();
1783 } 1785 }
1784 } else { 1786 } else {
1785 // Be careful to always use shifted_branch_offset only just before the 1787 // Be careful to always use shifted_branch_offset only just before the
1786 // branch instruction, as the location will be remember for patching the 1788 // branch instruction, as the location will be remember for patching the
1787 // target. 1789 // target.
1790 BlockTrampolinePoolScope block_trampoline_pool(this);
1788 switch (cond) { 1791 switch (cond) {
1789 case cc_always: 1792 case cc_always:
1790 b(offset); 1793 b(offset);
1791 break; 1794 break;
1792 case eq: 1795 case eq:
1793 // We don't want any other register but scratch clobbered. 1796 // We don't want any other register but scratch clobbered.
1794 ASSERT(!scratch.is(rs)); 1797 ASSERT(!scratch.is(rs));
1795 r2 = scratch; 1798 r2 = scratch;
1796 li(r2, rt); 1799 li(r2, rt);
1797 beq(rs, r2, offset); 1800 beq(rs, r2, offset);
(...skipping 124 matching lines...) Expand 10 before | Expand all | Expand 10 after
1922 1925
1923 void MacroAssembler::BranchShort(Label* L, Condition cond, Register rs, 1926 void MacroAssembler::BranchShort(Label* L, Condition cond, Register rs,
1924 const Operand& rt, 1927 const Operand& rt,
1925 BranchDelaySlot bdslot) { 1928 BranchDelaySlot bdslot) {
1926 BRANCH_ARGS_CHECK(cond, rs, rt); 1929 BRANCH_ARGS_CHECK(cond, rs, rt);
1927 1930
1928 int32_t offset; 1931 int32_t offset;
1929 Register r2 = no_reg; 1932 Register r2 = no_reg;
1930 Register scratch = at; 1933 Register scratch = at;
1931 if (rt.is_reg()) { 1934 if (rt.is_reg()) {
1935 BlockTrampolinePoolScope block_trampoline_pool(this);
1932 r2 = rt.rm_; 1936 r2 = rt.rm_;
1933 // Be careful to always use shifted_branch_offset only just before the 1937 // Be careful to always use shifted_branch_offset only just before the
1934 // branch instruction, as the location will be remember for patching the 1938 // branch instruction, as the location will be remember for patching the
1935 // target. 1939 // target.
1936 switch (cond) { 1940 switch (cond) {
1937 case cc_always: 1941 case cc_always:
1938 offset = shifted_branch_offset(L, false); 1942 offset = shifted_branch_offset(L, false);
1939 b(offset); 1943 b(offset);
1940 break; 1944 break;
1941 case eq: 1945 case eq:
(...skipping 86 matching lines...) Expand 10 before | Expand all | Expand 10 after
2028 beq(scratch, zero_reg, offset); 2032 beq(scratch, zero_reg, offset);
2029 } 2033 }
2030 break; 2034 break;
2031 default: 2035 default:
2032 UNREACHABLE(); 2036 UNREACHABLE();
2033 } 2037 }
2034 } else { 2038 } else {
2035 // Be careful to always use shifted_branch_offset only just before the 2039 // Be careful to always use shifted_branch_offset only just before the
2036 // branch instruction, as the location will be remember for patching the 2040 // branch instruction, as the location will be remember for patching the
2037 // target. 2041 // target.
2042 BlockTrampolinePoolScope block_trampoline_pool(this);
2038 switch (cond) { 2043 switch (cond) {
2039 case cc_always: 2044 case cc_always:
2040 offset = shifted_branch_offset(L, false); 2045 offset = shifted_branch_offset(L, false);
2041 b(offset); 2046 b(offset);
2042 break; 2047 break;
2043 case eq: 2048 case eq:
2044 ASSERT(!scratch.is(rs)); 2049 ASSERT(!scratch.is(rs));
2045 r2 = scratch; 2050 r2 = scratch;
2046 li(r2, rt); 2051 li(r2, rt);
2047 offset = shifted_branch_offset(L, false); 2052 offset = shifted_branch_offset(L, false);
(...skipping 216 matching lines...) Expand 10 before | Expand all | Expand 10 after
2264 Register r2 = no_reg; 2269 Register r2 = no_reg;
2265 Register scratch = at; 2270 Register scratch = at;
2266 2271
2267 if (rt.is_reg()) { 2272 if (rt.is_reg()) {
2268 r2 = rt.rm_; 2273 r2 = rt.rm_;
2269 } else if (cond != cc_always) { 2274 } else if (cond != cc_always) {
2270 r2 = scratch; 2275 r2 = scratch;
2271 li(r2, rt); 2276 li(r2, rt);
2272 } 2277 }
2273 2278
2274 switch (cond) { 2279 {
2275 case cc_always: 2280 BlockTrampolinePoolScope block_trampoline_pool(this);
2276 bal(offset); 2281 switch (cond) {
2277 break; 2282 case cc_always:
2278 case eq: 2283 bal(offset);
2279 bne(rs, r2, 2); 2284 break;
2280 nop(); 2285 case eq:
2281 bal(offset); 2286 bne(rs, r2, 2);
2282 break; 2287 nop();
2283 case ne: 2288 bal(offset);
2284 beq(rs, r2, 2); 2289 break;
2285 nop(); 2290 case ne:
2286 bal(offset); 2291 beq(rs, r2, 2);
2287 break; 2292 nop();
2293 bal(offset);
2294 break;
2288 2295
2289 // Signed comparison. 2296 // Signed comparison.
2290 case greater: 2297 case greater:
2291 slt(scratch, r2, rs); 2298 slt(scratch, r2, rs);
2292 addiu(scratch, scratch, -1); 2299 addiu(scratch, scratch, -1);
2293 bgezal(scratch, offset); 2300 bgezal(scratch, offset);
2294 break; 2301 break;
2295 case greater_equal: 2302 case greater_equal:
2296 slt(scratch, rs, r2); 2303 slt(scratch, rs, r2);
2297 addiu(scratch, scratch, -1); 2304 addiu(scratch, scratch, -1);
2298 bltzal(scratch, offset); 2305 bltzal(scratch, offset);
2299 break; 2306 break;
2300 case less: 2307 case less:
2301 slt(scratch, rs, r2); 2308 slt(scratch, rs, r2);
2302 addiu(scratch, scratch, -1); 2309 addiu(scratch, scratch, -1);
2303 bgezal(scratch, offset); 2310 bgezal(scratch, offset);
2304 break; 2311 break;
2305 case less_equal: 2312 case less_equal:
2306 slt(scratch, r2, rs); 2313 slt(scratch, r2, rs);
2307 addiu(scratch, scratch, -1); 2314 addiu(scratch, scratch, -1);
2308 bltzal(scratch, offset); 2315 bltzal(scratch, offset);
2309 break; 2316 break;
2310 2317
2311 // Unsigned comparison. 2318 // Unsigned comparison.
2312 case Ugreater: 2319 case Ugreater:
2313 sltu(scratch, r2, rs); 2320 sltu(scratch, r2, rs);
2314 addiu(scratch, scratch, -1); 2321 addiu(scratch, scratch, -1);
2315 bgezal(scratch, offset); 2322 bgezal(scratch, offset);
2316 break; 2323 break;
2317 case Ugreater_equal: 2324 case Ugreater_equal:
2318 sltu(scratch, rs, r2); 2325 sltu(scratch, rs, r2);
2319 addiu(scratch, scratch, -1); 2326 addiu(scratch, scratch, -1);
2320 bltzal(scratch, offset); 2327 bltzal(scratch, offset);
2321 break; 2328 break;
2322 case Uless: 2329 case Uless:
2323 sltu(scratch, rs, r2); 2330 sltu(scratch, rs, r2);
2324 addiu(scratch, scratch, -1); 2331 addiu(scratch, scratch, -1);
2325 bgezal(scratch, offset); 2332 bgezal(scratch, offset);
2326 break; 2333 break;
2327 case Uless_equal: 2334 case Uless_equal:
2328 sltu(scratch, r2, rs); 2335 sltu(scratch, r2, rs);
2329 addiu(scratch, scratch, -1); 2336 addiu(scratch, scratch, -1);
2330 bltzal(scratch, offset); 2337 bltzal(scratch, offset);
2331 break; 2338 break;
2332 2339
2333 default: 2340 default:
2334 UNREACHABLE(); 2341 UNREACHABLE();
2342 }
2335 } 2343 }
2336 // Emit a nop in the branch delay slot if required. 2344 // Emit a nop in the branch delay slot if required.
2337 if (bdslot == PROTECT) 2345 if (bdslot == PROTECT)
2338 nop(); 2346 nop();
2339 } 2347 }
2340 2348
2341 2349
2342 void MacroAssembler::BranchAndLinkShort(Label* L, BranchDelaySlot bdslot) { 2350 void MacroAssembler::BranchAndLinkShort(Label* L, BranchDelaySlot bdslot) {
2343 bal(shifted_branch_offset(L, false)); 2351 bal(shifted_branch_offset(L, false));
2344 2352
(...skipping 11 matching lines...) Expand all
2356 int32_t offset; 2364 int32_t offset;
2357 Register r2 = no_reg; 2365 Register r2 = no_reg;
2358 Register scratch = at; 2366 Register scratch = at;
2359 if (rt.is_reg()) { 2367 if (rt.is_reg()) {
2360 r2 = rt.rm_; 2368 r2 = rt.rm_;
2361 } else if (cond != cc_always) { 2369 } else if (cond != cc_always) {
2362 r2 = scratch; 2370 r2 = scratch;
2363 li(r2, rt); 2371 li(r2, rt);
2364 } 2372 }
2365 2373
2366 switch (cond) { 2374 {
2367 case cc_always: 2375 BlockTrampolinePoolScope block_trampoline_pool(this);
2368 offset = shifted_branch_offset(L, false); 2376 switch (cond) {
2369 bal(offset); 2377 case cc_always:
2370 break; 2378 offset = shifted_branch_offset(L, false);
2371 case eq: 2379 bal(offset);
2372 bne(rs, r2, 2); 2380 break;
2373 nop(); 2381 case eq:
2374 offset = shifted_branch_offset(L, false); 2382 bne(rs, r2, 2);
2375 bal(offset); 2383 nop();
2376 break; 2384 offset = shifted_branch_offset(L, false);
2377 case ne: 2385 bal(offset);
2378 beq(rs, r2, 2); 2386 break;
2379 nop(); 2387 case ne:
2380 offset = shifted_branch_offset(L, false); 2388 beq(rs, r2, 2);
2381 bal(offset); 2389 nop();
2382 break; 2390 offset = shifted_branch_offset(L, false);
2391 bal(offset);
2392 break;
2383 2393
2384 // Signed comparison. 2394 // Signed comparison.
2385 case greater: 2395 case greater:
2386 slt(scratch, r2, rs); 2396 slt(scratch, r2, rs);
2387 addiu(scratch, scratch, -1); 2397 addiu(scratch, scratch, -1);
2388 offset = shifted_branch_offset(L, false); 2398 offset = shifted_branch_offset(L, false);
2389 bgezal(scratch, offset); 2399 bgezal(scratch, offset);
2390 break; 2400 break;
2391 case greater_equal: 2401 case greater_equal:
2392 slt(scratch, rs, r2); 2402 slt(scratch, rs, r2);
2393 addiu(scratch, scratch, -1); 2403 addiu(scratch, scratch, -1);
2394 offset = shifted_branch_offset(L, false); 2404 offset = shifted_branch_offset(L, false);
2395 bltzal(scratch, offset); 2405 bltzal(scratch, offset);
2396 break; 2406 break;
2397 case less: 2407 case less:
2398 slt(scratch, rs, r2); 2408 slt(scratch, rs, r2);
2399 addiu(scratch, scratch, -1); 2409 addiu(scratch, scratch, -1);
2400 offset = shifted_branch_offset(L, false); 2410 offset = shifted_branch_offset(L, false);
2401 bgezal(scratch, offset); 2411 bgezal(scratch, offset);
2402 break; 2412 break;
2403 case less_equal: 2413 case less_equal:
2404 slt(scratch, r2, rs); 2414 slt(scratch, r2, rs);
2405 addiu(scratch, scratch, -1); 2415 addiu(scratch, scratch, -1);
2406 offset = shifted_branch_offset(L, false); 2416 offset = shifted_branch_offset(L, false);
2407 bltzal(scratch, offset); 2417 bltzal(scratch, offset);
2408 break; 2418 break;
2409 2419
2410 // Unsigned comparison. 2420 // Unsigned comparison.
2411 case Ugreater: 2421 case Ugreater:
2412 sltu(scratch, r2, rs); 2422 sltu(scratch, r2, rs);
2413 addiu(scratch, scratch, -1); 2423 addiu(scratch, scratch, -1);
2414 offset = shifted_branch_offset(L, false); 2424 offset = shifted_branch_offset(L, false);
2415 bgezal(scratch, offset); 2425 bgezal(scratch, offset);
2416 break; 2426 break;
2417 case Ugreater_equal: 2427 case Ugreater_equal:
2418 sltu(scratch, rs, r2); 2428 sltu(scratch, rs, r2);
2419 addiu(scratch, scratch, -1); 2429 addiu(scratch, scratch, -1);
2420 offset = shifted_branch_offset(L, false); 2430 offset = shifted_branch_offset(L, false);
2421 bltzal(scratch, offset); 2431 bltzal(scratch, offset);
2422 break; 2432 break;
2423 case Uless: 2433 case Uless:
2424 sltu(scratch, rs, r2); 2434 sltu(scratch, rs, r2);
2425 addiu(scratch, scratch, -1); 2435 addiu(scratch, scratch, -1);
2426 offset = shifted_branch_offset(L, false); 2436 offset = shifted_branch_offset(L, false);
2427 bgezal(scratch, offset); 2437 bgezal(scratch, offset);
2428 break; 2438 break;
2429 case Uless_equal: 2439 case Uless_equal:
2430 sltu(scratch, r2, rs); 2440 sltu(scratch, r2, rs);
2431 addiu(scratch, scratch, -1); 2441 addiu(scratch, scratch, -1);
2432 offset = shifted_branch_offset(L, false); 2442 offset = shifted_branch_offset(L, false);
2433 bltzal(scratch, offset); 2443 bltzal(scratch, offset);
2434 break; 2444 break;
2435 2445
2436 default: 2446 default:
2437 UNREACHABLE(); 2447 UNREACHABLE();
2448 }
2438 } 2449 }
2439
2440 // Check that offset could actually hold on an int16_t. 2450 // Check that offset could actually hold on an int16_t.
2441 ASSERT(is_int16(offset)); 2451 ASSERT(is_int16(offset));
2442 2452
2443 // Emit a nop in the branch delay slot if required. 2453 // Emit a nop in the branch delay slot if required.
2444 if (bdslot == PROTECT) 2454 if (bdslot == PROTECT)
2445 nop(); 2455 nop();
2446 } 2456 }
2447 2457
2448 2458
2449 void MacroAssembler::Jump(Register target, 2459 void MacroAssembler::Jump(Register target,
(...skipping 3103 matching lines...) Expand 10 before | Expand all | Expand 10 after
5553 opcode == BGTZL); 5563 opcode == BGTZL);
5554 opcode = (cond == eq) ? BEQ : BNE; 5564 opcode = (cond == eq) ? BEQ : BNE;
5555 instr = (instr & ~kOpcodeMask) | opcode; 5565 instr = (instr & ~kOpcodeMask) | opcode;
5556 masm_.emit(instr); 5566 masm_.emit(instr);
5557 } 5567 }
5558 5568
5559 5569
5560 } } // namespace v8::internal 5570 } } // namespace v8::internal
5561 5571
5562 #endif // V8_TARGET_ARCH_MIPS 5572 #endif // V8_TARGET_ARCH_MIPS
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