X87: [turbofan] Unify referencing of stack slots

X87: [turbofan] Unify referencing of stack slots

port cbbaf9ea6abbc0417ee5765a4c58f1dda939ead0 (r30224).

original commit message:

    [turbofan] Unify referencing of stack slots

    Previously, it was not possible to specify StackSlotOperands for all
    slots in both the caller and callee stacks. Specifically, the region
    of the callee's stack including the saved return address, frame
    pointer, function pointer and context pointer could not be addressed
    by the register allocator/gap resolver.

    In preparation for better tail call support, which will use the gap
    resolver to reconcile outgoing parameters, this change makes it
    possible to address all slots on the stack, because slots in the
    previously inaccessible dead zone may become parameter slots for
    outgoing tail calls. All caller stack slots are accessible as they
    were before, with slot -1 corresponding to the last stack
    parameter. Stack slot indices >= 0 access the callee stack, with slot
    0 corresponding to the callee's saved return address, 1 corresponding
    to the saved frame pointer, 2 corresponding to the current function
    context, 3 corresponding to the frame marker/JSFunction, and slots 4
    and above corresponding to spill slots.

    The following changes were specifically     needed:

    * Frame     has been changed to explicitly manage three areas of the
      callee frame, the fixed header, the spill slot area, and the
      callee-saved register area.
    * Conversions from stack slot indices to fp offsets all now go through
      a common bottleneck: OptimizedFrame::StackSlotOffsetRelativeToFp
    * The generation of deoptimization translation tables has been changed
      to support the new stack slot indexing scheme. Crankshaft, which
      doesn't support the new slot numbering in its register allocator,
      must adapt the indexes when creating translation tables.
    * Callee-saved parameters are now kept below spill slots, not above,
      to support saving only the optimal set of used registers, which is
      only known after register allocation is finished and spill slots
      have been allocated.

BUG=

Committed: https://crrev.com/97a48c538d9ea746b1a3f3c41c23fd07ec7d50ec
Cr-Commit-Position: refs/heads/master@{#30292}

[chunyang.dai, 2015-08-21 09:27:04]

chunyang.dai@intel.com changed reviewers:
+ weiliang.lin@intel.com

[chunyang.dai, 2015-08-21 09:27:05]

PTAL

[Weiliang, 2015-08-21 09:42:11]

The CQ bit was checked by weiliang.lin@intel.com

[Weiliang, 2015-08-21 09:42:11]

lgtm

[commit-bot: I haz the power, 2015-08-21 09:42:19]

CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1293103003/1
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1293103003/1

[commit-bot: I haz the power, 2015-08-21 10:26:20]

Committed patchset #1 (id:1)

[commit-bot: I haz the power, 2015-08-21 10:26:34]

Patchset 1 (id:??) landed as
https://crrev.com/97a48c538d9ea746b1a3f3c41c23fd07ec7d50ec
Cr-Commit-Position: refs/heads/master@{#30292}