Drops into Simulator Debugger only in a session that is already interactive.

runtime/vm/simulator_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include <math.h>  // for isnan.
 #include <setjmp.h>
 #include <stdlib.h>
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
@@ skipping 77 matching lines @@
 
 // The SimulatorDebugger class is used by the simulator while debugging
 // simulated ARM code.
 class SimulatorDebugger {
  public:
   explicit SimulatorDebugger(Simulator* sim);
   ~SimulatorDebugger();
 
   void Stop(Instr* instr, const char* message);
   void Debug();
+
   char* ReadLine(const char* prompt);
 
  private:
   static const int32_t kSimulatorBreakpointInstr =  // svc #kBreakpointSvcCode
     ((AL << kConditionShift) | (0xf << 24) | kBreakpointSvcCode);
   static const int32_t kNopInstr =  // nop
     ((AL << kConditionShift) | (0x32 << 20) | (0xf << 12));
 
   Simulator* sim_;
 
@@ skipping 178 matching lines @@
 void SimulatorDebugger::RedoBreakpoints() {
   if (sim_->break_pc_ != NULL) {
     sim_->break_pc_->SetInstructionBits(kSimulatorBreakpointInstr);
   }
 }
 
 
 void SimulatorDebugger::Debug() {
   intptr_t last_pc = -1;
   bool done = false;
-  bool decoded = true;
 
 #define COMMAND_SIZE 63
 #define ARG_SIZE 255
 
 #define STR(a) #a
 #define XSTR(a) STR(a)
 
   char cmd[COMMAND_SIZE + 1];
   char arg1[ARG_SIZE + 1];
   char arg2[ARG_SIZE + 1];
 
   // make sure to have a proper terminating character if reaching the limit
   cmd[COMMAND_SIZE] = 0;
   arg1[ARG_SIZE] = 0;
   arg2[ARG_SIZE] = 0;
 
   // Undo all set breakpoints while running in the debugger shell. This will
   // make them invisible to all commands.
   UndoBreakpoints();
 
   while (!done) {
     if (last_pc != sim_->get_pc()) {
       last_pc = sim_->get_pc();
-      decoded = Disassembler::Disassemble(last_pc, last_pc + Instr::kInstrSize);
+      Disassembler::Disassemble(last_pc, last_pc + Instr::kInstrSize);
     }
     char* line = ReadLine("sim> ");
     if (line == NULL) {
-      break;
+      FATAL("ReadLine failed");
     } else {
       // Use sscanf to parse the individual parts of the command line. At the
       // moment no command expects more than two parameters.
       int args = SScanF(line,
                         "%" XSTR(COMMAND_SIZE) "s "
                         "%" XSTR(ARG_SIZE) "s "
                         "%" XSTR(ARG_SIZE) "s",
                         cmd, arg1, arg2);
       if ((strcmp(cmd, "h") == 0) || (strcmp(cmd, "help") == 0)) {
         OS::Print("c/cont -- continue execution\n"
@@ skipping 11 matching lines @@
                   "pf/printfloat <sreg or *addr> -- print float value\n"
                   "pd/printdouble <dreg or *addr> -- print double value\n"
                   "po/printobject <*reg or *addr> -- print object\n"
                   "si/stepi -- single step an instruction\n"
                   "unstop -- if current pc is a stop instr make it a nop\n"
                   "q/quit -- Quit the debugger and exit the program\n");
       } else if ((strcmp(cmd, "quit") == 0) || (strcmp(cmd, "q") == 0)) {
         OS::Print("Quitting\n");
         OS::Exit(0);
       } else if ((strcmp(cmd, "si") == 0) || (strcmp(cmd, "stepi") == 0)) {
-        if (decoded) {
-          sim_->InstructionDecode(reinterpret_cast<Instr*>(sim_->get_pc()));
-        } else {
-          OS::Print("Instruction could not be decoded. Stepping disabled.\n");
-        }
+        sim_->InstructionDecode(reinterpret_cast<Instr*>(sim_->get_pc()));
       } else if ((strcmp(cmd, "c") == 0) || (strcmp(cmd, "cont") == 0)) {
-        if (decoded) {
-          // Execute the one instruction we broke at with breakpoints disabled.
-          sim_->InstructionDecode(reinterpret_cast<Instr*>(sim_->get_pc()));
-          // Leave the debugger shell.
-          done = true;
-        } else {
-          OS::Print("Instruction could not be decoded. Cannot continue.\n");
-        }
+        // Execute the one instruction we broke at with breakpoints disabled.
+        sim_->InstructionDecode(reinterpret_cast<Instr*>(sim_->get_pc()));
+        // Leave the debugger shell.
+        done = true;
       } else if ((strcmp(cmd, "p") == 0) || (strcmp(cmd, "print") == 0)) {
         if (args == 2) {
           uint32_t value;
           if (GetValue(arg1, &value)) {
             OS::Print("%s: %u 0x%x\n", arg1, value, value);
           } else {
             OS::Print("%s unrecognized\n", arg1);
           }
         } else {
           OS::Print("print <reg or value or *addr>\n");
@@ skipping 458 matching lines @@
   char buffer[64];
   snprintf(buffer, sizeof(buffer),
            "unaligned %s at 0x%"Px", pc=%p\n", msg, addr, instr);
   SimulatorDebugger dbg(this);
   dbg.Stop(instr, buffer);
   // The debugger will return control in non-interactive mode.
   FATAL("Cannot continue execution after unaligned access.");
 }
 
 
+void Simulator::UnimplementedInstruction(Instr* instr) {
+  char buffer[64];
+  snprintf(buffer, sizeof(buffer), "Unimplemented instruction: pc=%p\n", instr);
+  SimulatorDebugger dbg(this);
+  dbg.Stop(instr, buffer);
+  FATAL("Cannot continue execution after unimplemented instruction.");
+}
+
+
 int Simulator::ReadW(uword addr, Instr* instr) {
   static StatsCounter counter_read_w("Simulated word reads");
   counter_read_w.Increment();
   if ((addr & 3) == 0) {
     intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
     return *ptr;
   }
   UnalignedAccess("read", addr, instr);
   return 0;
 }
@@ skipping 221 matching lines @@
 
 // Addressing Mode 1 - Data-processing operands:
 // Get the value based on the shifter_operand with register.
 int32_t Simulator::GetShiftRm(Instr* instr, bool* carry_out) {
   Shift shift = instr->ShiftField();
   int shift_amount = instr->ShiftAmountField();
   int32_t result = get_register(instr->RmField());
   if (instr->Bit(4) == 0) {
     // by immediate
     if ((shift == ROR) && (shift_amount == 0)) {
-      UNIMPLEMENTED();
-      return result;
+      UnimplementedInstruction(instr);
     } else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) {
       shift_amount = 32;
     }
     switch (shift) {
       case ASR: {
         if (shift_amount == 0) {
           if (result < 0) {
             result = 0xffffffff;
             *carry_out = true;
           } else {
@@ skipping 27 matching lines @@
           uint32_t uresult = static_cast<uint32_t>(result);
           uresult >>= (shift_amount - 1);
           *carry_out = (uresult & 1) == 1;
           uresult >>= 1;
           result = static_cast<int32_t>(uresult);
         }
         break;
       }
 
       case ROR: {
-        UNIMPLEMENTED();
+        UnimplementedInstruction(instr);
         break;
       }
 
       default: {
         UNREACHABLE();
         break;
       }
     }
   } else {
     // by register
@@ skipping 51 matching lines @@
           *carry_out = (result < 0);
           result = 0;
         } else {
           *carry_out = false;
           result = 0;
         }
         break;
       }
 
       case ROR: {
-        UNIMPLEMENTED();
+        UnimplementedInstruction(instr);
         break;
       }
 
       default: {
         UNREACHABLE();
         break;
       }
     }
   }
   return result;
@@ skipping 246 matching lines @@
         case 7: {
           if (instr->Bits(21, 2) == 0x1) {
             // Format(instr, "bkpt'cond #'imm12_4");
             SimulatorDebugger dbg(this);
             set_pc(get_pc() + Instr::kInstrSize);
             char buffer[32];
             snprintf(buffer, sizeof(buffer), "bkpt #0x%x", instr->BkptField());
             dbg.Stop(instr, buffer);
           } else {
              // Format(instr, "smc'cond");
-            UNIMPLEMENTED();
+            UnimplementedInstruction(instr);
           }
           break;
         }
         default: {
-          UNIMPLEMENTED();
+          UnimplementedInstruction(instr);
           break;
         }
       }
     } else if (instr->IsMultiplyOrSyncPrimitive()) {
       if (instr->Bit(24) == 0) {
         // multiply instructions.
         Register rn = instr->RnField();
         Register rd = instr->RdField();
         Register rs = instr->RsField();
         Register rm = instr->RmField();
@@ skipping 39 matching lines @@
                 // Collapse bits 0..31 into bit 32 so that 32-bit Z check works.
                 hi_res |= 1;
               }
               ASSERT((result == 0) == (hi_res == 0));  // Z bit
               ASSERT(((result & (1LL << 63)) != 0) == (hi_res < 0));  // N bit
               SetNZFlags(hi_res);
             }
             break;
           }
           default: {
-            UNIMPLEMENTED();
+            UnimplementedInstruction(instr);
             break;
           }
         }
       } else {
         // synchronization primitives
         Register rd = instr->RdField();
         Register rn = instr->RnField();
         uword addr = get_register(rn);
         switch (instr->Bits(20, 4)) {
           case 8: {
             // Format(instr, "strex'cond 'rd, 'rm, ['rn]");
             if (IsIllegalAddress(addr)) {
               HandleIllegalAccess(addr, instr);
             } else {
               Register rm = instr->RmField();
               set_register(rd, WriteExclusiveW(addr, get_register(rm), instr));
             }
             break;
           }
           case 9: {
             // Format(instr, "ldrex'cond 'rd, ['rn]");
             if (IsIllegalAddress(addr)) {
               HandleIllegalAccess(addr, instr);
             } else {
               set_register(rd, ReadExclusiveW(addr, instr));
             }
             break;
           }
           default: {
-            UNIMPLEMENTED();
+            UnimplementedInstruction(instr);
             break;
           }
         }
       }
     } else if (instr->Bit(25) == 1) {
       // 16-bit immediate loads, msr (immediate), and hints
       switch (instr->Bits(20, 5)) {
         case 16:
         case 20: {
           uint16_t imm16 = instr->MovwField();
           Register rd = instr->RdField();
           if (instr->Bit(22) == 0) {
             // Format(instr, "movw'cond 'rd, #'imm4_12");
             set_register(rd, imm16);
           } else {
             // Format(instr, "movt'cond 'rd, #'imm4_12");
             set_register(rd, (get_register(rd) & 0xffff) | (imm16 << 16));
           }
           break;
         }
         case 18: {
           if ((instr->Bits(16, 4) == 0) && (instr->Bits(0, 8) == 0)) {
             // Format(instr, "nop'cond");
           } else {
-            UNIMPLEMENTED();
+            UnimplementedInstruction(instr);
           }
           break;
         }
         default: {
-          UNIMPLEMENTED();
+          UnimplementedInstruction(instr);
           break;
         }
       }
     } else {
       // extra load/store instructions
       Register rd = instr->RdField();
       Register rn = instr->RnField();
       int32_t rn_val = get_register(rn);
       uword addr = 0;
       bool write_back = false;
@@ skipping 107 matching lines @@
             int32_t val_high = get_register(rd1);
             WriteW(addr, val_low, instr);
             WriteW(addr + 4, val_high, instr);
           } else {
             int32_t val_low = ReadW(addr, instr);
             int32_t val_high = ReadW(addr + 4, instr);
             set_register(rd, val_low);
             set_register(rd1, val_high);
           }
         } else {
-          UNIMPLEMENTED();
+          UnimplementedInstruction(instr);
         }
       }
     }
   } else {
     Register rd = instr->RdField();
     Register rn = instr->RnField();
     int32_t rn_val = get_register(rn);
     int32_t shifter_operand = 0;
     bool shifter_carry_out = 0;
     if (instr->TypeField() == 0) {
@@ skipping 108 matching lines @@
       }
 
       case TST: {
         if (instr->HasS()) {
           // Format(instr, "tst'cond 'rn, 'shift_rm");
           // Format(instr, "tst'cond 'rn, 'imm");
           alu_out = rn_val & shifter_operand;
           SetNZFlags(alu_out);
           SetCFlag(shifter_carry_out);
         } else {
-          UNIMPLEMENTED();
+          UnimplementedInstruction(instr);
         }
         break;
       }
 
       case TEQ: {
         if (instr->HasS()) {
           // Format(instr, "teq'cond 'rn, 'shift_rm");
           // Format(instr, "teq'cond 'rn, 'imm");
           alu_out = rn_val ^ shifter_operand;
           SetNZFlags(alu_out);
           SetCFlag(shifter_carry_out);
         } else {
-          UNIMPLEMENTED();
+          UnimplementedInstruction(instr);
         }
         break;
       }
 
       case CMP: {
         if (instr->HasS()) {
           // Format(instr, "cmp'cond 'rn, 'shift_rm");
           // Format(instr, "cmp'cond 'rn, 'imm");
           alu_out = rn_val - shifter_operand;
           SetNZFlags(alu_out);
           SetCFlag(!BorrowFrom(rn_val, shifter_operand));
           SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, false));
         } else {
-          UNIMPLEMENTED();
+          UnimplementedInstruction(instr);
         }
         break;
       }
 
       case CMN: {
         if (instr->HasS()) {
           // Format(instr, "cmn'cond 'rn, 'shift_rm");
           // Format(instr, "cmn'cond 'rn, 'imm");
           alu_out = rn_val + shifter_operand;
           SetNZFlags(alu_out);
           SetCFlag(CarryFrom(rn_val, shifter_operand));
           SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, true));
         } else {
-          UNIMPLEMENTED();
+          UnimplementedInstruction(instr);
         }
         break;
       }
 
       case ORR: {
         // Format(instr, "orr'cond's 'rd, 'rn, 'shift_rm");
         // Format(instr, "orr'cond's 'rd, 'rn, 'imm");
         alu_out = rn_val | shifter_operand;
         set_register(rd, alu_out);
         if (instr->HasS()) {
@@ skipping 363 matching lines @@
             // Format(instr, "vstmd'cond'pu 'rn'w, 'dlist");
             int64_t dd_val = bit_cast<int64_t, double>(get_dregister(dd));
             WriteW(addr, Utils::Low32Bits(dd_val), instr);
             WriteW(addr + 4, Utils::High32Bits(dd_val), instr);
           }
           addr += 8;
         }
       }
     }
   } else {
-    UNIMPLEMENTED();
+    UnimplementedInstruction(instr);
   }
 }
 
 
 void Simulator::DecodeType7(Instr* instr) {
   if (instr->Bit(24) == 1) {
     // Format(instr, "svc #'svc");
     SupervisorCall(instr);
   } else if (instr->IsVFPDataProcessingOrSingleTransfer()) {
     if (instr->Bit(4) == 0) {
@@ skipping 15 matching lines @@
         sd = kNoSRegister;
         sn = kNoSRegister;
         sm = kNoSRegister;
         dd = instr->DdField();
         dn = instr->DnField();
         dm = instr->DmField();
       }
       switch (instr->Bits(20, 4) & 0xb) {
         case 1:  // vnmla, vnmls, vnmul
         default: {
-          UNIMPLEMENTED();
+          UnimplementedInstruction(instr);
           break;
         }
         case 0: {  // vmla, vmls floating-point
           if (instr->Bit(8) == 0) {
             float addend = get_sregister(sn) * get_sregister(sm);
             float sd_val = get_sregister(sd);
             if (instr->Bit(6) == 0) {
               // Format(instr, "vmlas'cond 'sd, 'sn, 'sm");
             } else {
               // Format(instr, "vmlss'cond 'sd, 'sn, 'sm");
@@ skipping 81 matching lines @@
                   if (instr->Bit(8) == 0) {
                     // Format(instr, "vabss'cond 'sd, 'sm");
                     set_sregister(sd, fabsf(get_sregister(sm)));
                   } else {
                     // Format(instr, "vabsd'cond 'dd, 'dm");
                     set_dregister(dd, fabs(get_dregister(dm)));
                   }
                   break;
                 }
                 default: {
-                  UNIMPLEMENTED();
+                  UnimplementedInstruction(instr);
                   break;
                 }
               }
               break;
             }
             case 1: {  // vneg, vsqrt
               switch (instr->Bits(6, 2)) {
                 case 1: {  // vneg
                   if (instr->Bit(8) == 0) {
                     // Format(instr, "vnegs'cond 'sd, 'sm");
                     set_sregister(sd, -get_sregister(sm));
                   } else {
                     // Format(instr, "vnegd'cond 'dd, 'dm");
                     set_dregister(dd, -get_dregister(dm));
                   }
                   break;
                 }
                 case 3: {  // vsqrt
                   if (instr->Bit(8) == 0) {
                     // Format(instr, "vsqrts'cond 'sd, 'sm");
                     set_sregister(sd, sqrtf(get_sregister(sm)));
                   } else {
                     // Format(instr, "vsqrtd'cond 'dd, 'dm");
                     set_dregister(dd, sqrt(get_dregister(dm)));
                   }
                   break;
                 }
                 default: {
-                  UNIMPLEMENTED();
+                  UnimplementedInstruction(instr);
                   break;
                 }
               }
               break;
             }
             case 4:  // vcmp, vcmpe
             case 5: {  // vcmp #0.0, vcmpe #0.0
               if (instr->Bit(7) == 1) {  // vcmpe
-                UNIMPLEMENTED();
+                UnimplementedInstruction(instr);
               } else {
                 fp_n_flag_ = false;
                 fp_z_flag_ = false;
                 fp_c_flag_ = false;
                 fp_v_flag_ = false;
                 if (instr->Bit(8) == 0) {  // vcmps
                   float sd_val = get_sregister(sd);
                   float sm_val;
                   if (instr->Bit(16) == 0) {
                     // Format(instr, "vcmps'cond 'sd, 'sm");
@@ skipping 82 matching lines @@
                 set_dregister(dd, dd_val);
               }
               break;
             }
             case 12:
             case 13: {  // vcvt, vcvtr between floating-point and integer
               // We do not need to record exceptions in the FPSCR cumulative
               // flags, because we do not use them.
               if (instr->Bit(7) == 0) {
                 // We only support round-to-zero mode
-                UNIMPLEMENTED();
+                UnimplementedInstruction(instr);
                 break;
               }
               int32_t id_val = 0;
               uint32_t ud_val = 0;
               if (instr->Bit(8) == 0) {
                 float sm_val = get_sregister(sm);
                 if (instr->Bit(16) == 0) {
                   // Format(instr, "vcvtus'cond 'sd, 'sm");
                   if (sm_val >= INT_MAX) {
                     ud_val = INT_MAX;
@@ skipping 43 matching lines @@
               break;
             }
             case 2:  // vcvtb, vcvtt
             case 3:  // vcvtb, vcvtt
             case 9:  // undefined
             case 10:  // vcvt between floating-point and fixed-point
             case 11:  // vcvt between floating-point and fixed-point
             case 14:  // vcvt between floating-point and fixed-point
             case 15:  // vcvt between floating-point and fixed-point
             default: {
-              UNIMPLEMENTED();
+              UnimplementedInstruction(instr);
               break;
             }
           }
         }
         break;
       }
     } else {
       // 8, 16, or 32-bit Transfer between ARM Core and VFP
       if ((instr->Bits(21, 3) == 0) && (instr->Bit(8) == 0)) {
         Register rd = instr->RdField();
         SRegister sn = instr->SnField();
         if (instr->Bit(20) == 0) {
           // Format(instr, "vmovs'cond 'sn, 'rd");
           set_sregister(sn, bit_cast<float, int32_t>(get_register(rd)));
         } else {
           // Format(instr, "vmovr'cond 'rd, 'sn");
           set_register(rd, bit_cast<int32_t, float>(get_sregister(sn)));
         }
       } else if ((instr->Bits(20, 4) == 0xf) && (instr->Bit(8) == 0) &&
                  (instr->Bits(12, 4) == 0xf)) {
         // Format(instr, "vmstat'cond");
         n_flag_ = fp_n_flag_;
         z_flag_ = fp_z_flag_;
         c_flag_ = fp_c_flag_;
         v_flag_ = fp_v_flag_;
       } else {
-        UNIMPLEMENTED();
+        UnimplementedInstruction(instr);
       }
     }
   } else if (instr->IsMrcIdIsar0()) {
     // mrc of ID_ISAR0.
     Register rd = instr->RdField();
     if (CPUFeatures::integer_division_supported()) {
       set_register(rd, 0x02100010);  // sim has sdiv, udiv, bkpt and clz.
     } else {
       set_register(rd, 0x00100010);  // simulator has only bkpt and clz.
     }
   } else {
-    UNIMPLEMENTED();
+    UnimplementedInstruction(instr);
   }
 }
 
 
 // Executes the current instruction.
 void Simulator::InstructionDecode(Instr* instr) {
   pc_modified_ = false;
   if (FLAG_trace_sim) {
     const uword start = reinterpret_cast<uword>(instr);
     const uword end = start + Instr::kInstrSize;
     Disassembler::Disassemble(start, end);
   }
   if (instr->ConditionField() == kSpecialCondition) {
     if (instr->InstructionBits() == static_cast<int32_t>(0xf57ff01f)) {
       // Format(instr, "clrex");
       ClearExclusive();
     } else {
-      UNIMPLEMENTED();
+      UnimplementedInstruction(instr);
     }
   } else if (ConditionallyExecute(instr)) {
     switch (instr->TypeField()) {
       case 0:
       case 1: {
         DecodeType01(instr);
         break;
       }
       case 2: {
         DecodeType2(instr);
@@ skipping 13 matching lines @@
       }
       case 6: {
         DecodeType6(instr);
         break;
       }
       case 7: {
         DecodeType7(instr);
         break;
       }
       default: {
-        UNIMPLEMENTED();
+        // Type field is three bits.
+        UNREACHABLE();
         break;
       }
     }
   }
   if (!pc_modified_) {
     set_register(PC, reinterpret_cast<int32_t>(instr) + Instr::kInstrSize);
   }
 }
 
 
@@ skipping 20 matching lines @@
     }
   } else {
     // FLAG_stop_sim_at is at the non-default value. Stop in the debugger when
     // we reach the particular instruction count.
     while (program_counter != kEndSimulatingPC) {
       Instr* instr = reinterpret_cast<Instr*>(program_counter);
       icount_++;
       counter_instructions.Increment();
       if (icount_ == FLAG_stop_sim_at) {
         SimulatorDebugger dbg(this);
-        dbg.Debug();
+        dbg.Stop(instr, "Instruction count reached");
       } else if (IsIllegalAddress(program_counter)) {
         HandleIllegalAccess(program_counter, instr);
       } else {
         InstructionDecode(instr);
       }
       program_counter = get_pc();
     }
   }
 }
 
@@ skipping 100 matching lines @@
   // isolate->ChangeStateToGeneratedCode();
   set_register(kExceptionObjectReg, bit_cast<int32_t>(object.raw()));
   buf->Longjmp();
 }
 
 }  // namespace dart
 
 #endif  // !defined(HOST_ARCH_ARM)
 
 #endif  // defined TARGET_ARCH_ARM