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Unified Diff: src/register-configuration.h

Issue 1287383003: Re-reland: Remove register index/code indirection (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Fix MIPS tests again Created 5 years, 2 months ago
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Index: src/register-configuration.h
diff --git a/src/register-configuration.h b/src/register-configuration.h
new file mode 100644
index 0000000000000000000000000000000000000000..f12bc7c07c6dfb4beb79477f5a88ce16502b4c71
--- /dev/null
+++ b/src/register-configuration.h
@@ -0,0 +1,88 @@
+// Copyright 2014 the V8 project authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE file.
+
+#ifndef V8_COMPILER_REGISTER_CONFIGURATION_H_
+#define V8_COMPILER_REGISTER_CONFIGURATION_H_
+
+#include "src/base/macros.h"
+
+namespace v8 {
+namespace internal {
+
+// An architecture independent representation of the sets of registers available
+// for instruction creation.
+class RegisterConfiguration {
+ public:
+ // Architecture independent maxes.
+ static const int kMaxGeneralRegisters = 32;
+ static const int kMaxDoubleRegisters = 32;
+
+ static const RegisterConfiguration* ArchDefault();
+
+ RegisterConfiguration(int num_general_registers, int num_double_registers,
+ int num_allocatable_general_registers,
+ int num_allocatable_double_registers,
+ int num_allocatable_aliased_double_registers,
+ const int* allocatable_general_codes,
+ const int* allocatable_double_codes,
+ char const* const* general_names,
+ char const* const* double_names);
+
+ int num_general_registers() const { return num_general_registers_; }
+ int num_double_registers() const { return num_double_registers_; }
+ int num_allocatable_general_registers() const {
+ return num_allocatable_general_registers_;
+ }
+ int num_allocatable_double_registers() const {
+ return num_allocatable_double_registers_;
+ }
+ // TODO(turbofan): This is a temporary work-around required because our
+ // register allocator does not yet support the aliasing of single/double
+ // registers on ARM.
+ int num_allocatable_aliased_double_registers() const {
+ return num_allocatable_aliased_double_registers_;
+ }
+ int32_t allocatable_general_codes_mask() const {
+ return allocatable_general_codes_mask_;
+ }
+ int32_t allocatable_double_codes_mask() const {
+ return allocatable_double_codes_mask_;
+ }
+ int GetAllocatableGeneralCode(int index) const {
+ return allocatable_general_codes_[index];
+ }
+ int GetAllocatableDoubleCode(int index) const {
+ return allocatable_double_codes_[index];
+ }
+ const char* GetGeneralRegisterName(int code) const {
+ return general_register_names_[code];
+ }
+ const char* GetDoubleRegisterName(int code) const {
+ return double_register_names_[code];
+ }
+ const int* allocatable_general_codes() const {
+ return allocatable_general_codes_;
+ }
+ const int* allocatable_double_codes() const {
+ return allocatable_double_codes_;
+ }
+
+ private:
+ const int num_general_registers_;
+ const int num_double_registers_;
+ int num_allocatable_general_registers_;
+ int num_allocatable_double_registers_;
+ int num_allocatable_aliased_double_registers_;
+ int32_t allocatable_general_codes_mask_;
+ int32_t allocatable_double_codes_mask_;
+ const int* allocatable_general_codes_;
+ const int* allocatable_double_codes_;
+ char const* const* general_register_names_;
+ char const* const* double_register_names_;
+};
+
+} // namespace internal
+} // namespace v8
+
+#endif // V8_COMPILER_REGISTER_CONFIGURATION_H_
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