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Issue 1287383003: Re-reland: Remove register index/code indirection (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Merge with ToT Created 5 years, 3 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/base/adapters.h" 5 #include "src/base/adapters.h"
6 #include "src/compiler/linkage.h" 6 #include "src/compiler/linkage.h"
7 #include "src/compiler/register-allocator.h" 7 #include "src/compiler/register-allocator.h"
8 #include "src/string-stream.h" 8 #include "src/string-stream.h"
9 9
10 namespace v8 { 10 namespace v8 {
11 namespace internal { 11 namespace internal {
12 namespace compiler { 12 namespace compiler {
13 13
14 #define TRACE(...) \ 14 #define TRACE(...) \
15 do { \ 15 do { \
16 if (FLAG_trace_alloc) PrintF(__VA_ARGS__); \ 16 if (FLAG_trace_alloc) PrintF(__VA_ARGS__); \
17 } while (false) 17 } while (false)
18 18
19 19
20 namespace { 20 namespace {
21 21
22 void RemoveElement(ZoneVector<LiveRange*>* v, LiveRange* range) { 22 void RemoveElement(ZoneVector<LiveRange*>* v, LiveRange* range) {
23 auto it = std::find(v->begin(), v->end(), range); 23 auto it = std::find(v->begin(), v->end(), range);
24 DCHECK(it != v->end()); 24 DCHECK(it != v->end());
25 v->erase(it); 25 v->erase(it);
26 } 26 }
27 27
28 28
29 int GetRegisterCount(const RegisterConfiguration* cfg, RegisterKind kind) { 29 int GetRegisterCount(const RegisterConfiguration* cfg, RegisterKind kind) {
30 return kind == DOUBLE_REGISTERS ? cfg->num_aliased_double_registers() 30 return kind == DOUBLE_REGISTERS ? cfg->num_double_registers()
31 : cfg->num_general_registers(); 31 : cfg->num_general_registers();
32 } 32 }
33 33
34 34
35 int GetAllocatableRegisterCount(const RegisterConfiguration* cfg,
36 RegisterKind kind) {
37 return kind == DOUBLE_REGISTERS
38 ? cfg->num_allocatable_aliased_double_registers()
39 : cfg->num_allocatable_general_registers();
40 }
41
42
43 const int* GetAllocatableRegisterCodes(const RegisterConfiguration* cfg,
44 RegisterKind kind) {
45 return kind == DOUBLE_REGISTERS ? cfg->allocatable_double_codes()
46 : cfg->allocatable_general_codes();
47 }
48
49
35 const InstructionBlock* GetContainingLoop(const InstructionSequence* sequence, 50 const InstructionBlock* GetContainingLoop(const InstructionSequence* sequence,
36 const InstructionBlock* block) { 51 const InstructionBlock* block) {
37 auto index = block->loop_header(); 52 auto index = block->loop_header();
38 if (!index.IsValid()) return nullptr; 53 if (!index.IsValid()) return nullptr;
39 return sequence->InstructionBlockAt(index); 54 return sequence->InstructionBlockAt(index);
40 } 55 }
41 56
42 57
43 const InstructionBlock* GetInstructionBlock(const InstructionSequence* code, 58 const InstructionBlock* GetInstructionBlock(const InstructionSequence* code,
44 LifetimePosition pos) { 59 LifetimePosition pos) {
45 return code->GetInstructionBlock(pos.ToInstructionIndex()); 60 return code->GetInstructionBlock(pos.ToInstructionIndex());
46 } 61 }
47 62
48 63
49 Instruction* GetLastInstruction(InstructionSequence* code, 64 Instruction* GetLastInstruction(InstructionSequence* code,
50 const InstructionBlock* block) { 65 const InstructionBlock* block) {
51 return code->InstructionAt(block->last_instruction_index()); 66 return code->InstructionAt(block->last_instruction_index());
52 } 67 }
53 68
54 69
55 bool IsOutputRegisterOf(Instruction* instr, int index) { 70 bool IsOutputRegisterOf(Instruction* instr, Register reg) {
56 for (size_t i = 0; i < instr->OutputCount(); i++) { 71 for (size_t i = 0; i < instr->OutputCount(); i++) {
57 auto output = instr->OutputAt(i); 72 auto output = instr->OutputAt(i);
58 if (output->IsRegister() && 73 if (output->IsRegister() &&
59 RegisterOperand::cast(output)->index() == index) { 74 RegisterOperand::cast(output)->GetRegister().is(reg)) {
60 return true; 75 return true;
61 } 76 }
62 } 77 }
63 return false; 78 return false;
64 } 79 }
65 80
66 81
67 bool IsOutputDoubleRegisterOf(Instruction* instr, int index) { 82 bool IsOutputDoubleRegisterOf(Instruction* instr, DoubleRegister reg) {
68 for (size_t i = 0; i < instr->OutputCount(); i++) { 83 for (size_t i = 0; i < instr->OutputCount(); i++) {
69 auto output = instr->OutputAt(i); 84 auto output = instr->OutputAt(i);
70 if (output->IsDoubleRegister() && 85 if (output->IsDoubleRegister() &&
71 DoubleRegisterOperand::cast(output)->index() == index) { 86 DoubleRegisterOperand::cast(output)->GetDoubleRegister().is(reg)) {
72 return true; 87 return true;
73 } 88 }
74 } 89 }
75 return false; 90 return false;
76 } 91 }
77 92
78 93
79 // TODO(dcarney): fix frame to allow frame accesses to half size location. 94 // TODO(dcarney): fix frame to allow frame accesses to half size location.
80 int GetByteWidth(MachineType machine_type) { 95 int GetByteWidth(MachineType machine_type) {
81 DCHECK_EQ(RepresentationOf(machine_type), machine_type); 96 DCHECK_EQ(RepresentationOf(machine_type), machine_type);
(...skipping 40 matching lines...) Expand 10 before | Expand all | Expand 10 after
122 DCHECK(pos_.IsValid()); 137 DCHECK(pos_.IsValid());
123 } 138 }
124 139
125 140
126 bool UsePosition::HasHint() const { 141 bool UsePosition::HasHint() const {
127 int hint_register; 142 int hint_register;
128 return HintRegister(&hint_register); 143 return HintRegister(&hint_register);
129 } 144 }
130 145
131 146
132 bool UsePosition::HintRegister(int* register_index) const { 147 bool UsePosition::HintRegister(int* register_code) const {
133 if (hint_ == nullptr) return false; 148 if (hint_ == nullptr) return false;
134 switch (HintTypeField::decode(flags_)) { 149 switch (HintTypeField::decode(flags_)) {
135 case UsePositionHintType::kNone: 150 case UsePositionHintType::kNone:
136 case UsePositionHintType::kUnresolved: 151 case UsePositionHintType::kUnresolved:
137 return false; 152 return false;
138 case UsePositionHintType::kUsePos: { 153 case UsePositionHintType::kUsePos: {
139 auto use_pos = reinterpret_cast<UsePosition*>(hint_); 154 auto use_pos = reinterpret_cast<UsePosition*>(hint_);
140 int assigned_register = AssignedRegisterField::decode(use_pos->flags_); 155 int assigned_register = AssignedRegisterField::decode(use_pos->flags_);
141 if (assigned_register == kUnassignedRegister) return false; 156 if (assigned_register == kUnassignedRegister) return false;
142 *register_index = assigned_register; 157 *register_code = assigned_register;
143 return true; 158 return true;
144 } 159 }
145 case UsePositionHintType::kOperand: { 160 case UsePositionHintType::kOperand: {
146 auto operand = reinterpret_cast<InstructionOperand*>(hint_); 161 auto operand = reinterpret_cast<InstructionOperand*>(hint_);
147 int assigned_register = AllocatedOperand::cast(operand)->index(); 162 int assigned_register =
148 *register_index = assigned_register; 163 operand->IsRegister()
164 ? RegisterOperand::cast(operand)->GetRegister().code()
165 : DoubleRegisterOperand::cast(operand)
166 ->GetDoubleRegister()
167 .code();
168 *register_code = assigned_register;
149 return true; 169 return true;
150 } 170 }
151 case UsePositionHintType::kPhi: { 171 case UsePositionHintType::kPhi: {
152 auto phi = reinterpret_cast<RegisterAllocationData::PhiMapValue*>(hint_); 172 auto phi = reinterpret_cast<RegisterAllocationData::PhiMapValue*>(hint_);
153 int assigned_register = phi->assigned_register(); 173 int assigned_register = phi->assigned_register();
154 if (assigned_register == kUnassignedRegister) return false; 174 if (assigned_register == kUnassignedRegister) return false;
155 *register_index = assigned_register; 175 *register_code = assigned_register;
156 return true; 176 return true;
157 } 177 }
158 } 178 }
159 UNREACHABLE(); 179 UNREACHABLE();
160 return false; 180 return false;
161 } 181 }
162 182
163 183
164 UsePositionHintType UsePosition::HintTypeForOperand( 184 UsePositionHintType UsePosition::HintTypeForOperand(
165 const InstructionOperand& op) { 185 const InstructionOperand& op) {
(...skipping 1040 matching lines...) Expand 10 before | Expand all | Expand 10 after
1206 1226
1207 RegisterAllocationData::RegisterAllocationData( 1227 RegisterAllocationData::RegisterAllocationData(
1208 const RegisterConfiguration* config, Zone* zone, Frame* frame, 1228 const RegisterConfiguration* config, Zone* zone, Frame* frame,
1209 InstructionSequence* code, const char* debug_name) 1229 InstructionSequence* code, const char* debug_name)
1210 : allocation_zone_(zone), 1230 : allocation_zone_(zone),
1211 frame_(frame), 1231 frame_(frame),
1212 code_(code), 1232 code_(code),
1213 debug_name_(debug_name), 1233 debug_name_(debug_name),
1214 config_(config), 1234 config_(config),
1215 phi_map_(allocation_zone()), 1235 phi_map_(allocation_zone()),
1236 allocatable_codes_(this->config()->num_general_registers(), -1,
1237 allocation_zone()),
1238 allocatable_double_codes_(this->config()->num_double_registers(), -1,
1239 allocation_zone()),
1216 live_in_sets_(code->InstructionBlockCount(), nullptr, allocation_zone()), 1240 live_in_sets_(code->InstructionBlockCount(), nullptr, allocation_zone()),
1217 live_out_sets_(code->InstructionBlockCount(), nullptr, allocation_zone()), 1241 live_out_sets_(code->InstructionBlockCount(), nullptr, allocation_zone()),
1218 live_ranges_(code->VirtualRegisterCount() * 2, nullptr, 1242 live_ranges_(code->VirtualRegisterCount() * 2, nullptr,
1219 allocation_zone()), 1243 allocation_zone()),
1220 fixed_live_ranges_(this->config()->num_general_registers(), nullptr, 1244 fixed_live_ranges_(this->config()->num_general_registers(), nullptr,
1221 allocation_zone()), 1245 allocation_zone()),
1222 fixed_double_live_ranges_(this->config()->num_double_registers(), nullptr, 1246 fixed_double_live_ranges_(this->config()->num_double_registers(), nullptr,
1223 allocation_zone()), 1247 allocation_zone()),
1224 spill_ranges_(code->VirtualRegisterCount(), nullptr, allocation_zone()), 1248 spill_ranges_(code->VirtualRegisterCount(), nullptr, allocation_zone()),
1225 delayed_references_(allocation_zone()), 1249 delayed_references_(allocation_zone()),
1226 assigned_registers_(nullptr), 1250 assigned_registers_(nullptr),
1227 assigned_double_registers_(nullptr), 1251 assigned_double_registers_(nullptr),
1228 virtual_register_count_(code->VirtualRegisterCount()) { 1252 virtual_register_count_(code->VirtualRegisterCount()) {
1229 DCHECK(this->config()->num_general_registers() <= 1253 DCHECK(this->config()->num_general_registers() <=
1230 RegisterConfiguration::kMaxGeneralRegisters); 1254 RegisterConfiguration::kMaxGeneralRegisters);
1231 DCHECK(this->config()->num_double_registers() <= 1255 DCHECK(this->config()->num_double_registers() <=
1232 RegisterConfiguration::kMaxDoubleRegisters); 1256 RegisterConfiguration::kMaxDoubleRegisters);
1233 assigned_registers_ = new (code_zone()) 1257 assigned_registers_ = new (code_zone())
1234 BitVector(this->config()->num_general_registers(), code_zone()); 1258 BitVector(this->config()->num_general_registers(), code_zone());
1235 assigned_double_registers_ = new (code_zone()) 1259 assigned_double_registers_ = new (code_zone())
1236 BitVector(this->config()->num_aliased_double_registers(), code_zone()); 1260 BitVector(this->config()->num_double_registers(), code_zone());
1237 this->frame()->SetAllocatedRegisters(assigned_registers_); 1261 this->frame()->SetAllocatedRegisters(assigned_registers_);
1238 this->frame()->SetAllocatedDoubleRegisters(assigned_double_registers_); 1262 this->frame()->SetAllocatedDoubleRegisters(assigned_double_registers_);
1239 } 1263 }
1240 1264
1241 1265
1242 MoveOperands* RegisterAllocationData::AddGapMove( 1266 MoveOperands* RegisterAllocationData::AddGapMove(
1243 int index, Instruction::GapPosition position, 1267 int index, Instruction::GapPosition position,
1244 const InstructionOperand& from, const InstructionOperand& to) { 1268 const InstructionOperand& from, const InstructionOperand& to) {
1245 auto instr = code()->InstructionAt(index); 1269 auto instr = code()->InstructionAt(index);
1246 auto moves = instr->GetOrCreateParallelMove(position, code_zone()); 1270 auto moves = instr->GetOrCreateParallelMove(position, code_zone());
(...skipping 518 matching lines...) Expand 10 before | Expand all | Expand 10 after
1765 DCHECK(result->IsFixed()); 1789 DCHECK(result->IsFixed());
1766 result->set_assigned_register(index); 1790 result->set_assigned_register(index);
1767 data()->MarkAllocated(GENERAL_REGISTERS, index); 1791 data()->MarkAllocated(GENERAL_REGISTERS, index);
1768 data()->fixed_live_ranges()[index] = result; 1792 data()->fixed_live_ranges()[index] = result;
1769 } 1793 }
1770 return result; 1794 return result;
1771 } 1795 }
1772 1796
1773 1797
1774 TopLevelLiveRange* LiveRangeBuilder::FixedDoubleLiveRangeFor(int index) { 1798 TopLevelLiveRange* LiveRangeBuilder::FixedDoubleLiveRangeFor(int index) {
1775 DCHECK(index < config()->num_aliased_double_registers()); 1799 DCHECK(index < config()->num_double_registers());
1776 auto result = data()->fixed_double_live_ranges()[index]; 1800 auto result = data()->fixed_double_live_ranges()[index];
1777 if (result == nullptr) { 1801 if (result == nullptr) {
1778 result = data()->NewLiveRange(FixedDoubleLiveRangeID(index), kRepFloat64); 1802 result = data()->NewLiveRange(FixedDoubleLiveRangeID(index), kRepFloat64);
1779 DCHECK(result->IsFixed()); 1803 DCHECK(result->IsFixed());
1780 result->set_assigned_register(index); 1804 result->set_assigned_register(index);
1781 data()->MarkAllocated(DOUBLE_REGISTERS, index); 1805 data()->MarkAllocated(DOUBLE_REGISTERS, index);
1782 data()->fixed_double_live_ranges()[index] = result; 1806 data()->fixed_double_live_ranges()[index] = result;
1783 } 1807 }
1784 return result; 1808 return result;
1785 } 1809 }
1786 1810
1787 1811
1788 TopLevelLiveRange* LiveRangeBuilder::LiveRangeFor(InstructionOperand* operand) { 1812 TopLevelLiveRange* LiveRangeBuilder::LiveRangeFor(InstructionOperand* operand) {
1789 if (operand->IsUnallocated()) { 1813 if (operand->IsUnallocated()) {
1790 return data()->GetOrCreateLiveRangeFor( 1814 return data()->GetOrCreateLiveRangeFor(
1791 UnallocatedOperand::cast(operand)->virtual_register()); 1815 UnallocatedOperand::cast(operand)->virtual_register());
1792 } else if (operand->IsConstant()) { 1816 } else if (operand->IsConstant()) {
1793 return data()->GetOrCreateLiveRangeFor( 1817 return data()->GetOrCreateLiveRangeFor(
1794 ConstantOperand::cast(operand)->virtual_register()); 1818 ConstantOperand::cast(operand)->virtual_register());
1795 } else if (operand->IsRegister()) { 1819 } else if (operand->IsRegister()) {
1796 return FixedLiveRangeFor(RegisterOperand::cast(operand)->index()); 1820 return FixedLiveRangeFor(
1821 RegisterOperand::cast(operand)->GetRegister().code());
1797 } else if (operand->IsDoubleRegister()) { 1822 } else if (operand->IsDoubleRegister()) {
1798 return FixedDoubleLiveRangeFor( 1823 return FixedDoubleLiveRangeFor(
1799 DoubleRegisterOperand::cast(operand)->index()); 1824 DoubleRegisterOperand::cast(operand)->GetDoubleRegister().code());
1800 } else { 1825 } else {
1801 return nullptr; 1826 return nullptr;
1802 } 1827 }
1803 } 1828 }
1804 1829
1805 1830
1806 UsePosition* LiveRangeBuilder::NewUsePosition(LifetimePosition pos, 1831 UsePosition* LiveRangeBuilder::NewUsePosition(LifetimePosition pos,
1807 InstructionOperand* operand, 1832 InstructionOperand* operand,
1808 void* hint, 1833 void* hint,
1809 UsePositionHintType hint_type) { 1834 UsePositionHintType hint_type) {
(...skipping 69 matching lines...) Expand 10 before | Expand all | Expand 10 after
1879 // exception value. 1904 // exception value.
1880 // TODO(mtrofin): should we explore an explicit opcode for 1905 // TODO(mtrofin): should we explore an explicit opcode for
1881 // the first instruction in the handler? 1906 // the first instruction in the handler?
1882 Define(LifetimePosition::GapFromInstructionIndex(index), output); 1907 Define(LifetimePosition::GapFromInstructionIndex(index), output);
1883 } else { 1908 } else {
1884 Define(curr_position, output); 1909 Define(curr_position, output);
1885 } 1910 }
1886 } 1911 }
1887 1912
1888 if (instr->ClobbersRegisters()) { 1913 if (instr->ClobbersRegisters()) {
1889 for (int i = 0; i < config()->num_general_registers(); ++i) { 1914 for (int i = 0; i < config()->num_allocatable_general_registers(); ++i) {
1890 if (!IsOutputRegisterOf(instr, i)) { 1915 int code = config()->GetAllocatableGeneralCode(i);
1891 auto range = FixedLiveRangeFor(i); 1916 if (!IsOutputRegisterOf(instr, Register::from_code(code))) {
1917 auto range = FixedLiveRangeFor(code);
1892 range->AddUseInterval(curr_position, curr_position.End(), 1918 range->AddUseInterval(curr_position, curr_position.End(),
1893 allocation_zone()); 1919 allocation_zone());
1894 } 1920 }
1895 } 1921 }
1896 } 1922 }
1897 1923
1898 if (instr->ClobbersDoubleRegisters()) { 1924 if (instr->ClobbersDoubleRegisters()) {
1899 for (int i = 0; i < config()->num_aliased_double_registers(); ++i) { 1925 for (int i = 0; i < config()->num_allocatable_aliased_double_registers();
1900 if (!IsOutputDoubleRegisterOf(instr, i)) { 1926 ++i) {
1901 auto range = FixedDoubleLiveRangeFor(i); 1927 int code = config()->GetAllocatableDoubleCode(i);
1928 if (!IsOutputDoubleRegisterOf(instr, DoubleRegister::from_code(code))) {
1929 auto range = FixedDoubleLiveRangeFor(code);
1902 range->AddUseInterval(curr_position, curr_position.End(), 1930 range->AddUseInterval(curr_position, curr_position.End(),
1903 allocation_zone()); 1931 allocation_zone());
1904 } 1932 }
1905 } 1933 }
1906 } 1934 }
1907 1935
1908 for (size_t i = 0; i < instr->InputCount(); i++) { 1936 for (size_t i = 0; i < instr->InputCount(); i++) {
1909 auto input = instr->InputAt(i); 1937 auto input = instr->InputAt(i);
1910 if (input->IsImmediate()) continue; // Ignore immediates. 1938 if (input->IsImmediate()) continue; // Ignore immediates.
1911 LifetimePosition use_pos; 1939 LifetimePosition use_pos;
(...skipping 225 matching lines...) Expand 10 before | Expand all | Expand 10 after
2137 for (LiveRange* current : data()->live_ranges()) { 2165 for (LiveRange* current : data()->live_ranges()) {
2138 if (current != nullptr) current->Verify(); 2166 if (current != nullptr) current->Verify();
2139 } 2167 }
2140 } 2168 }
2141 2169
2142 2170
2143 RegisterAllocator::RegisterAllocator(RegisterAllocationData* data, 2171 RegisterAllocator::RegisterAllocator(RegisterAllocationData* data,
2144 RegisterKind kind) 2172 RegisterKind kind)
2145 : data_(data), 2173 : data_(data),
2146 mode_(kind), 2174 mode_(kind),
2147 num_registers_(GetRegisterCount(data->config(), kind)) {} 2175 num_registers_(GetRegisterCount(data->config(), kind)),
2176 num_allocatable_registers_(
2177 GetAllocatableRegisterCount(data->config(), kind)),
2178 allocatable_register_codes_(
2179 GetAllocatableRegisterCodes(data->config(), kind)) {}
2148 2180
2149 2181
2150 LiveRange* RegisterAllocator::SplitRangeAt(LiveRange* range, 2182 LiveRange* RegisterAllocator::SplitRangeAt(LiveRange* range,
2151 LifetimePosition pos) { 2183 LifetimePosition pos) {
2152 DCHECK(!range->TopLevel()->IsFixed()); 2184 DCHECK(!range->TopLevel()->IsFixed());
2153 TRACE("Splitting live range %d:%d at %d\n", range->TopLevel()->vreg(), 2185 TRACE("Splitting live range %d:%d at %d\n", range->TopLevel()->vreg(),
2154 range->relative_id(), pos.value()); 2186 range->relative_id(), pos.value());
2155 2187
2156 if (pos <= range->Start()) return range; 2188 if (pos <= range->Start()) return range;
2157 2189
(...skipping 102 matching lines...) Expand 10 before | Expand all | Expand 10 after
2260 } 2292 }
2261 2293
2262 2294
2263 const ZoneVector<TopLevelLiveRange*>& RegisterAllocator::GetFixedRegisters() 2295 const ZoneVector<TopLevelLiveRange*>& RegisterAllocator::GetFixedRegisters()
2264 const { 2296 const {
2265 return mode() == DOUBLE_REGISTERS ? data()->fixed_double_live_ranges() 2297 return mode() == DOUBLE_REGISTERS ? data()->fixed_double_live_ranges()
2266 : data()->fixed_live_ranges(); 2298 : data()->fixed_live_ranges();
2267 } 2299 }
2268 2300
2269 2301
2270 const char* RegisterAllocator::RegisterName(int allocation_index) const { 2302 const char* RegisterAllocator::RegisterName(int register_code) const {
2271 if (mode() == GENERAL_REGISTERS) { 2303 if (mode() == GENERAL_REGISTERS) {
2272 return data()->config()->general_register_name(allocation_index); 2304 return data()->config()->GetGeneralRegisterName(register_code);
2273 } else { 2305 } else {
2274 return data()->config()->double_register_name(allocation_index); 2306 return data()->config()->GetDoubleRegisterName(register_code);
2275 } 2307 }
2276 } 2308 }
2277 2309
2278 2310
2279 LinearScanAllocator::LinearScanAllocator(RegisterAllocationData* data, 2311 LinearScanAllocator::LinearScanAllocator(RegisterAllocationData* data,
2280 RegisterKind kind, Zone* local_zone) 2312 RegisterKind kind, Zone* local_zone)
2281 : RegisterAllocator(data, kind), 2313 : RegisterAllocator(data, kind),
2282 unhandled_live_ranges_(local_zone), 2314 unhandled_live_ranges_(local_zone),
2283 active_live_ranges_(local_zone), 2315 active_live_ranges_(local_zone),
2284 inactive_live_ranges_(local_zone) { 2316 inactive_live_ranges_(local_zone) {
(...skipping 218 matching lines...) Expand 10 before | Expand all | Expand 10 after
2503 bool LinearScanAllocator::TryAllocateFreeReg(LiveRange* current) { 2535 bool LinearScanAllocator::TryAllocateFreeReg(LiveRange* current) {
2504 LifetimePosition free_until_pos[RegisterConfiguration::kMaxDoubleRegisters]; 2536 LifetimePosition free_until_pos[RegisterConfiguration::kMaxDoubleRegisters];
2505 2537
2506 for (int i = 0; i < num_registers(); i++) { 2538 for (int i = 0; i < num_registers(); i++) {
2507 free_until_pos[i] = LifetimePosition::MaxPosition(); 2539 free_until_pos[i] = LifetimePosition::MaxPosition();
2508 } 2540 }
2509 2541
2510 for (auto cur_active : active_live_ranges()) { 2542 for (auto cur_active : active_live_ranges()) {
2511 free_until_pos[cur_active->assigned_register()] = 2543 free_until_pos[cur_active->assigned_register()] =
2512 LifetimePosition::GapFromInstructionIndex(0); 2544 LifetimePosition::GapFromInstructionIndex(0);
2545 TRACE("Register %s is free until pos %d (1)\n",
2546 RegisterName(cur_active->assigned_register()),
2547 LifetimePosition::GapFromInstructionIndex(0).value());
2513 } 2548 }
2514 2549
2515 for (auto cur_inactive : inactive_live_ranges()) { 2550 for (auto cur_inactive : inactive_live_ranges()) {
2516 DCHECK(cur_inactive->End() > current->Start()); 2551 DCHECK(cur_inactive->End() > current->Start());
2517 auto next_intersection = cur_inactive->FirstIntersection(current); 2552 auto next_intersection = cur_inactive->FirstIntersection(current);
2518 if (!next_intersection.IsValid()) continue; 2553 if (!next_intersection.IsValid()) continue;
2519 int cur_reg = cur_inactive->assigned_register(); 2554 int cur_reg = cur_inactive->assigned_register();
2520 free_until_pos[cur_reg] = Min(free_until_pos[cur_reg], next_intersection); 2555 free_until_pos[cur_reg] = Min(free_until_pos[cur_reg], next_intersection);
2556 TRACE("Register %s is free until pos %d (2)\n", RegisterName(cur_reg),
2557 Min(free_until_pos[cur_reg], next_intersection).value());
2521 } 2558 }
2522 2559
2523 int hint_register; 2560 int hint_register;
2524 if (current->FirstHintPosition(&hint_register) != nullptr) { 2561 if (current->FirstHintPosition(&hint_register) != nullptr) {
2525 TRACE( 2562 TRACE(
2526 "Found reg hint %s (free until [%d) for live range %d:%d (end %d[).\n", 2563 "Found reg hint %s (free until [%d) for live range %d:%d (end %d[).\n",
2527 RegisterName(hint_register), free_until_pos[hint_register].value(), 2564 RegisterName(hint_register), free_until_pos[hint_register].value(),
2528 current->TopLevel()->vreg(), current->relative_id(), 2565 current->TopLevel()->vreg(), current->relative_id(),
2529 current->End().value()); 2566 current->End().value());
2530 2567
2531 // The desired register is free until the end of the current live range. 2568 // The desired register is free until the end of the current live range.
2532 if (free_until_pos[hint_register] >= current->End()) { 2569 if (free_until_pos[hint_register] >= current->End()) {
2533 TRACE("Assigning preferred reg %s to live range %d:%d\n", 2570 TRACE("Assigning preferred reg %s to live range %d:%d\n",
2534 RegisterName(hint_register), current->TopLevel()->vreg(), 2571 RegisterName(hint_register), current->TopLevel()->vreg(),
2535 current->relative_id()); 2572 current->relative_id());
2536 SetLiveRangeAssignedRegister(current, hint_register); 2573 SetLiveRangeAssignedRegister(current, hint_register);
2537 return true; 2574 return true;
2538 } 2575 }
2539 } 2576 }
2540 2577
2541 // Find the register which stays free for the longest time. 2578 // Find the register which stays free for the longest time.
2542 int reg = 0; 2579 int reg = allocatable_register_code(0);
2543 for (int i = 1; i < num_registers(); ++i) { 2580 for (int i = 1; i < num_alloctable_registers(); ++i) {
2544 if (free_until_pos[i] > free_until_pos[reg]) { 2581 int code = allocatable_register_code(i);
2545 reg = i; 2582 if (free_until_pos[code] > free_until_pos[reg]) {
2583 reg = code;
2546 } 2584 }
2547 } 2585 }
2548 2586
2549 auto pos = free_until_pos[reg]; 2587 auto pos = free_until_pos[reg];
2550 2588
2551 if (pos <= current->Start()) { 2589 if (pos <= current->Start()) {
2552 // All registers are blocked. 2590 // All registers are blocked.
2553 return false; 2591 return false;
2554 } 2592 }
2555 2593
(...skipping 54 matching lines...) Expand 10 before | Expand all | Expand 10 after
2610 if (!next_intersection.IsValid()) continue; 2648 if (!next_intersection.IsValid()) continue;
2611 int cur_reg = range->assigned_register(); 2649 int cur_reg = range->assigned_register();
2612 if (range->TopLevel()->IsFixed()) { 2650 if (range->TopLevel()->IsFixed()) {
2613 block_pos[cur_reg] = Min(block_pos[cur_reg], next_intersection); 2651 block_pos[cur_reg] = Min(block_pos[cur_reg], next_intersection);
2614 use_pos[cur_reg] = Min(block_pos[cur_reg], use_pos[cur_reg]); 2652 use_pos[cur_reg] = Min(block_pos[cur_reg], use_pos[cur_reg]);
2615 } else { 2653 } else {
2616 use_pos[cur_reg] = Min(use_pos[cur_reg], next_intersection); 2654 use_pos[cur_reg] = Min(use_pos[cur_reg], next_intersection);
2617 } 2655 }
2618 } 2656 }
2619 2657
2620 int reg = 0; 2658 int reg = allocatable_register_code(0);
2621 for (int i = 1; i < num_registers(); ++i) { 2659 for (int i = 1; i < num_alloctable_registers(); ++i) {
2622 if (use_pos[i] > use_pos[reg]) { 2660 int code = allocatable_register_code(i);
2623 reg = i; 2661 if (use_pos[code] > use_pos[reg]) {
2662 reg = code;
2624 } 2663 }
2625 } 2664 }
2626 2665
2627 auto pos = use_pos[reg]; 2666 auto pos = use_pos[reg];
2628 2667
2629 if (pos < register_use->pos()) { 2668 if (pos < register_use->pos()) {
2630 // All registers are blocked before the first use that requires a register. 2669 // All registers are blocked before the first use that requires a register.
2631 // Spill starting part of live range up to that use. 2670 // Spill starting part of live range up to that use.
2632 SpillBetween(current, current->Start(), register_use->pos()); 2671 SpillBetween(current, current->Start(), register_use->pos());
2633 return; 2672 return;
(...skipping 686 matching lines...) Expand 10 before | Expand all | Expand 10 after
3320 auto eliminate = moves->PrepareInsertAfter(move); 3359 auto eliminate = moves->PrepareInsertAfter(move);
3321 to_insert.push_back(move); 3360 to_insert.push_back(move);
3322 if (eliminate != nullptr) to_eliminate.push_back(eliminate); 3361 if (eliminate != nullptr) to_eliminate.push_back(eliminate);
3323 } 3362 }
3324 } 3363 }
3325 3364
3326 3365
3327 } // namespace compiler 3366 } // namespace compiler
3328 } // namespace internal 3367 } // namespace internal
3329 } // namespace v8 3368 } // namespace v8
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