Re-reland: Remove register index/code indirection

test/cctest/compiler/test-run-native-calls.cc

 // Copyright 2015 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/assembler.h"
 #include "src/codegen.h"
 #include "src/compiler/linkage.h"
 #include "src/compiler/machine-type.h"
 #include "src/compiler/raw-machine-assembler.h"
+#include "src/register-configuration.h"
 
 #include "test/cctest/cctest.h"
 #include "test/cctest/compiler/codegen-tester.h"
 #include "test/cctest/compiler/graph-builder-tester.h"
 #include "test/cctest/compiler/value-helper.h"
 
 using namespace v8::base;
 using namespace v8::internal;
 using namespace v8::internal::compiler;
 
 typedef RawMachineAssembler::Label MLabel;
 
 #if V8_TARGET_ARCH_ARM64
 // TODO(titzer): fix native stack parameters on arm64
 #define DISABLE_NATIVE_STACK_PARAMS true
 #else
 #define DISABLE_NATIVE_STACK_PARAMS false
 #endif
 
 namespace {
 typedef float float32;
 typedef double float64;
 
 // Picks a representative pair of integers from the given range.
 // If there are less than {max_pairs} possible pairs, do them all, otherwise try
 // to select a representative set.
 class Pairs {
  public:
-  Pairs(int max_pairs, int range)
+  Pairs(int max_pairs, int range, const int* codes)
       : range_(range),
+        codes_(codes),
         max_pairs_(std::min(max_pairs, range_ * range_)),
         counter_(0) {}
 
   bool More() { return counter_ < max_pairs_; }
 
   void Next(int* r0, int* r1, bool same_is_ok) {
     do {
       // Find the next pair.
       if (exhaustive()) {
-        *r0 = counter_ % range_;
-        *r1 = counter_ / range_;
+        *r0 = codes_[counter_ % range_];
+        *r1 = codes_[counter_ / range_];
       } else {
         // Try each integer at least once for both r0 and r1.
         int index = counter_ / 2;
         if (counter_ & 1) {
-          *r0 = index % range_;
-          *r1 = index / range_;
+          *r0 = codes_[index % range_];
+          *r1 = codes_[index / range_];
         } else {
-          *r1 = index % range_;
-          *r0 = index / range_;
+          *r1 = codes_[index % range_];
+          *r0 = codes_[index / range_];
         }
       }
       counter_++;
-      if (same_is_ok) break;
-      if (*r0 == *r1) {
-        if (counter_ >= max_pairs_) {
-          // For the last hurrah, reg#0 with reg#n-1
-          *r0 = 0;
-          *r1 = range_ - 1;
-          break;
-        }
+      if ((same_is_ok) || (*r0 != *r1)) break;
+      if (counter_ == max_pairs_) {
+        // For the last hurrah, reg#0 with reg#n-1
+        *r0 = codes_[0];
+        *r1 = codes_[range_ - 1];
+        break;
       }
     } while (true);
-
-    DCHECK(*r0 >= 0 && *r0 < range_);
-    DCHECK(*r1 >= 0 && *r1 < range_);
   }
 
  private:
   int range_;
+  const int* codes_;
   int max_pairs_;
   int counter_;
   bool exhaustive() { return max_pairs_ == (range_ * range_); }
 };
 
 
 // Pairs of general purpose registers.
 class RegisterPairs : public Pairs {
  public:
-  RegisterPairs() : Pairs(100, Register::kMaxNumAllocatableRegisters) {}
+  RegisterPairs()
+      : Pairs(
+            100, RegisterConfiguration::ArchDefault()
+                     ->num_allocatable_general_registers(),
+            RegisterConfiguration::ArchDefault()->allocatable_general_codes()) {
+  }
 };
 
 
 // Pairs of double registers.
 class Float32RegisterPairs : public Pairs {
  public:
   Float32RegisterPairs()
-      : Pairs(100, DoubleRegister::NumAllocatableAliasedRegisters()) {}
+      : Pairs(
+            100, RegisterConfiguration::ArchDefault()
+                     ->num_allocatable_aliased_double_registers(),
+            RegisterConfiguration::ArchDefault()->allocatable_double_codes()) {}
 };
 
 
 // Pairs of double registers.
 class Float64RegisterPairs : public Pairs {
  public:
   Float64RegisterPairs()
-      : Pairs(100, DoubleRegister::NumAllocatableAliasedRegisters()) {}
+      : Pairs(
+            100, RegisterConfiguration::ArchDefault()
+                     ->num_allocatable_aliased_double_registers(),
+            RegisterConfiguration::ArchDefault()->allocatable_double_codes()) {}
 };
 
 
 // Helper for allocating either an GP or FP reg, or the next stack slot.
 struct Allocator {
   Allocator(int* gp, int gpc, int* fp, int fpc)
       : gp_count(gpc),
         gp_offset(0),
         gp_regs(gp),
         fp_count(fpc),
@@ skipping 501 matching lines @@
     Allocator params(parray, 2, nullptr, 0);
     Allocator rets(rarray, 1, nullptr, 0);
     RegisterConfig config(params, rets);
     CallDescriptor* desc = config.Create(&zone, &sig);
     TestInt32Sub(desc);
   }
 }
 
 
 // Separate tests for parallelization.
-#define TEST_INT32_SUB_WITH_RET(x)                                             \
-  TEST(Run_Int32Sub_all_allocatable_pairs_##x) {                               \
-    if (Register::kMaxNumAllocatableRegisters > x) Test_RunInt32SubWithRet(x); \
+#define TEST_INT32_SUB_WITH_RET(x)                \
+  TEST(Run_Int32Sub_all_allocatable_pairs_##x) {  \
+    if (x < Register::kNumRegisters &&            \
+        Register::from_code(x).IsAllocatable()) { \
+      Test_RunInt32SubWithRet(x);                 \
+    }                                             \
   }
 
 
 TEST_INT32_SUB_WITH_RET(0)
 TEST_INT32_SUB_WITH_RET(1)
 TEST_INT32_SUB_WITH_RET(2)
 TEST_INT32_SUB_WITH_RET(3)
 TEST_INT32_SUB_WITH_RET(4)
 TEST_INT32_SUB_WITH_RET(5)
 TEST_INT32_SUB_WITH_RET(6)
@@ skipping 77 matching lines @@
   for (int i = 0; i < ParamCount(desc); i++) {
     result += static_cast<uint32_t>(input[i]) * coeff[i];
   }
   return static_cast<int32_t>(result);
 }
 
 
 static void Test_Int32_WeightedSum_of_size(int count) {
   if (DISABLE_NATIVE_STACK_PARAMS) return;
   Int32Signature sig(count);
-  for (int p0 = 0; p0 < Register::kMaxNumAllocatableRegisters; p0++) {
-    Zone zone;
+  for (int p0 = 0; p0 < Register::kNumRegisters; p0++) {
+    if (Register::from_code(p0).IsAllocatable()) {
+      Zone zone;
 
-    int parray[] = {p0};
-    int rarray[] = {0};
-    Allocator params(parray, 1, nullptr, 0);
-    Allocator rets(rarray, 1, nullptr, 0);
-    RegisterConfig config(params, rets);
-    CallDescriptor* desc = config.Create(&zone, &sig);
-    Run_Computation<int32_t>(desc, Build_Int32_WeightedSum,
-                             Compute_Int32_WeightedSum, 257 + count);
+      int parray[] = {p0};
+      int rarray[] = {0};
+      Allocator params(parray, 1, nullptr, 0);
+      Allocator rets(rarray, 1, nullptr, 0);
+      RegisterConfig config(params, rets);
+      CallDescriptor* desc = config.Create(&zone, &sig);
+      Run_Computation<int32_t>(desc, Build_Int32_WeightedSum,
+                               Compute_Int32_WeightedSum, 257 + count);
+    }
   }
 }
 
 
 // Separate tests for parallelization.
 #define TEST_INT32_WEIGHTEDSUM(x) \
   TEST(Run_Int32_WeightedSum_##x) { Test_Int32_WeightedSum_of_size(x); }
 
 
 TEST_INT32_WEIGHTEDSUM(1)
@@ skipping 64 matching lines @@
 TEST_INT32_SELECT(6)
 TEST_INT32_SELECT(11)
 TEST_INT32_SELECT(15)
 TEST_INT32_SELECT(19)
 TEST_INT32_SELECT(45)
 TEST_INT32_SELECT(62)
 TEST_INT32_SELECT(63)
 
 
 TEST(Int64Select_registers) {
-  if (Register::kMaxNumAllocatableRegisters < 2) return;
+  if (RegisterConfiguration::ArchDefault()
+          ->num_allocatable_general_registers() < 2)
+    return;
   if (kPointerSize < 8) return;  // TODO(titzer): int64 on 32-bit platforms
 
   int rarray[] = {0};
   ArgsBuffer<int64_t>::Sig sig(2);
 
   RegisterPairs pairs;
   Zone zone;
   while (pairs.More()) {
     int parray[2];
     pairs.Next(&parray[0], &parray[1], false);
     Allocator params(parray, 2, nullptr, 0);
     Allocator rets(rarray, 1, nullptr, 0);
     RegisterConfig config(params, rets);
 
     CallDescriptor* desc = config.Create(&zone, &sig);
     RunSelect<int64_t, 0>(desc);
     RunSelect<int64_t, 1>(desc);
   }
 }
 
 
 TEST(Float32Select_registers) {
-  if (RegisterConfiguration::ArchDefault()->num_double_registers() < 2) return;
+  if (RegisterConfiguration::ArchDefault()->num_allocatable_double_registers() <
+      2) {
+    return;
+  }
 
   int rarray[] = {0};
   ArgsBuffer<float32>::Sig sig(2);
 
   Float32RegisterPairs pairs;
   Zone zone;
   while (pairs.More()) {
     int parray[2];
     pairs.Next(&parray[0], &parray[1], false);
     Allocator params(nullptr, 0, parray, 2);
     Allocator rets(nullptr, 0, rarray, 1);
     RegisterConfig config(params, rets);
 
     CallDescriptor* desc = config.Create(&zone, &sig);
     RunSelect<float32, 0>(desc);
     RunSelect<float32, 1>(desc);
   }
 }
 
 
 TEST(Float64Select_registers) {
-  if (RegisterConfiguration::ArchDefault()->num_double_registers() < 2) return;
-
+  if (RegisterConfiguration::ArchDefault()->num_allocatable_double_registers() <
+      2)
+    return;
+  if (RegisterConfiguration::ArchDefault()
+          ->num_allocatable_general_registers() < 2)
+    return;
   int rarray[] = {0};
   ArgsBuffer<float64>::Sig sig(2);
 
   Float64RegisterPairs pairs;
   Zone zone;
   while (pairs.More()) {
     int parray[2];
     pairs.Next(&parray[0], &parray[1], false);
     Allocator params(nullptr, 0, parray, 2);
     Allocator rets(nullptr, 0, rarray, 1);
@@ skipping 213 matching lines @@
       }
     }
   }
 }
 
 
 TEST(MixedParams_0) { MixedParamTest(0); }
 TEST(MixedParams_1) { MixedParamTest(1); }
 TEST(MixedParams_2) { MixedParamTest(2); }
 TEST(MixedParams_3) { MixedParamTest(3); }