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Issue 1287383003: Re-reland: Remove register index/code indirection (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Updated to ToT Created 5 years, 3 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/base/adapters.h" 5 #include "src/base/adapters.h"
6 #include "src/compiler/linkage.h" 6 #include "src/compiler/linkage.h"
7 #include "src/compiler/register-allocator.h" 7 #include "src/compiler/register-allocator.h"
8 #include "src/string-stream.h" 8 #include "src/string-stream.h"
9 9
10 namespace v8 { 10 namespace v8 {
11 namespace internal { 11 namespace internal {
12 namespace compiler { 12 namespace compiler {
13 13
14 #define TRACE(...) \ 14 #define TRACE(...) \
15 do { \ 15 do { \
16 if (FLAG_trace_alloc) PrintF(__VA_ARGS__); \ 16 if (FLAG_trace_alloc) PrintF(__VA_ARGS__); \
17 } while (false) 17 } while (false)
18 18
19 19
20 namespace { 20 namespace {
21 21
22 void RemoveElement(ZoneVector<LiveRange*>* v, LiveRange* range) { 22 void RemoveElement(ZoneVector<LiveRange*>* v, LiveRange* range) {
23 auto it = std::find(v->begin(), v->end(), range); 23 auto it = std::find(v->begin(), v->end(), range);
24 DCHECK(it != v->end()); 24 DCHECK(it != v->end());
25 v->erase(it); 25 v->erase(it);
26 } 26 }
27 27
28 28
29 int GetRegisterCount(const RegisterConfiguration* cfg, RegisterKind kind) { 29 int GetRegisterCount(const RegisterConfiguration* cfg, RegisterKind kind) {
30 return kind == DOUBLE_REGISTERS ? cfg->num_aliased_double_registers() 30 return kind == DOUBLE_REGISTERS ? cfg->num_double_registers()
31 : cfg->num_general_registers(); 31 : cfg->num_general_registers();
32 } 32 }
33 33
34 34
35 int GetAllocatableRegisterCount(const RegisterConfiguration* cfg,
36 RegisterKind kind) {
37 return kind == DOUBLE_REGISTERS
38 ? cfg->num_allocatable_aliased_double_registers()
39 : cfg->num_allocatable_general_registers();
40 }
41
42
43 const int* GetAllocatableRegisterCodes(const RegisterConfiguration* cfg,
44 RegisterKind kind) {
45 return kind == DOUBLE_REGISTERS ? cfg->allocatable_double_codes()
46 : cfg->allocatable_general_codes();
47 }
48
49
35 const InstructionBlock* GetContainingLoop(const InstructionSequence* sequence, 50 const InstructionBlock* GetContainingLoop(const InstructionSequence* sequence,
36 const InstructionBlock* block) { 51 const InstructionBlock* block) {
37 auto index = block->loop_header(); 52 auto index = block->loop_header();
38 if (!index.IsValid()) return nullptr; 53 if (!index.IsValid()) return nullptr;
39 return sequence->InstructionBlockAt(index); 54 return sequence->InstructionBlockAt(index);
40 } 55 }
41 56
42 57
43 const InstructionBlock* GetInstructionBlock(const InstructionSequence* code, 58 const InstructionBlock* GetInstructionBlock(const InstructionSequence* code,
44 LifetimePosition pos) { 59 LifetimePosition pos) {
45 return code->GetInstructionBlock(pos.ToInstructionIndex()); 60 return code->GetInstructionBlock(pos.ToInstructionIndex());
46 } 61 }
47 62
48 63
49 Instruction* GetLastInstruction(InstructionSequence* code, 64 Instruction* GetLastInstruction(InstructionSequence* code,
50 const InstructionBlock* block) { 65 const InstructionBlock* block) {
51 return code->InstructionAt(block->last_instruction_index()); 66 return code->InstructionAt(block->last_instruction_index());
52 } 67 }
53 68
54 69
55 bool IsOutputRegisterOf(Instruction* instr, int index) { 70 bool IsOutputRegisterOf(Instruction* instr, Register reg) {
56 for (size_t i = 0; i < instr->OutputCount(); i++) { 71 for (size_t i = 0; i < instr->OutputCount(); i++) {
57 auto output = instr->OutputAt(i); 72 auto output = instr->OutputAt(i);
58 if (output->IsRegister() && 73 if (output->IsRegister() &&
59 RegisterOperand::cast(output)->index() == index) { 74 RegisterOperand::cast(output)->GetRegister().is(reg)) {
60 return true; 75 return true;
61 } 76 }
62 } 77 }
63 return false; 78 return false;
64 } 79 }
65 80
66 81
67 bool IsOutputDoubleRegisterOf(Instruction* instr, int index) { 82 bool IsOutputDoubleRegisterOf(Instruction* instr, DoubleRegister reg) {
68 for (size_t i = 0; i < instr->OutputCount(); i++) { 83 for (size_t i = 0; i < instr->OutputCount(); i++) {
69 auto output = instr->OutputAt(i); 84 auto output = instr->OutputAt(i);
70 if (output->IsDoubleRegister() && 85 if (output->IsDoubleRegister() &&
71 DoubleRegisterOperand::cast(output)->index() == index) { 86 DoubleRegisterOperand::cast(output)->GetDoubleRegister().is(reg)) {
72 return true; 87 return true;
73 } 88 }
74 } 89 }
75 return false; 90 return false;
76 } 91 }
77 92
78 93
79 // TODO(dcarney): fix frame to allow frame accesses to half size location. 94 // TODO(dcarney): fix frame to allow frame accesses to half size location.
80 int GetByteWidth(MachineType machine_type) { 95 int GetByteWidth(MachineType machine_type) {
81 DCHECK_EQ(RepresentationOf(machine_type), machine_type); 96 DCHECK_EQ(RepresentationOf(machine_type), machine_type);
(...skipping 40 matching lines...) Expand 10 before | Expand all | Expand 10 after
122 DCHECK(pos_.IsValid()); 137 DCHECK(pos_.IsValid());
123 } 138 }
124 139
125 140
126 bool UsePosition::HasHint() const { 141 bool UsePosition::HasHint() const {
127 int hint_register; 142 int hint_register;
128 return HintRegister(&hint_register); 143 return HintRegister(&hint_register);
129 } 144 }
130 145
131 146
132 bool UsePosition::HintRegister(int* register_index) const { 147 bool UsePosition::HintRegister(int* register_code) const {
133 if (hint_ == nullptr) return false; 148 if (hint_ == nullptr) return false;
134 switch (HintTypeField::decode(flags_)) { 149 switch (HintTypeField::decode(flags_)) {
135 case UsePositionHintType::kNone: 150 case UsePositionHintType::kNone:
136 case UsePositionHintType::kUnresolved: 151 case UsePositionHintType::kUnresolved:
137 return false; 152 return false;
138 case UsePositionHintType::kUsePos: { 153 case UsePositionHintType::kUsePos: {
139 auto use_pos = reinterpret_cast<UsePosition*>(hint_); 154 auto use_pos = reinterpret_cast<UsePosition*>(hint_);
140 int assigned_register = AssignedRegisterField::decode(use_pos->flags_); 155 int assigned_register = AssignedRegisterField::decode(use_pos->flags_);
141 if (assigned_register == kUnassignedRegister) return false; 156 if (assigned_register == kUnassignedRegister) return false;
142 *register_index = assigned_register; 157 *register_code = assigned_register;
143 return true; 158 return true;
144 } 159 }
145 case UsePositionHintType::kOperand: { 160 case UsePositionHintType::kOperand: {
146 auto operand = reinterpret_cast<InstructionOperand*>(hint_); 161 auto operand = reinterpret_cast<InstructionOperand*>(hint_);
147 int assigned_register = AllocatedOperand::cast(operand)->index(); 162 int assigned_register =
148 *register_index = assigned_register; 163 operand->IsRegister()
164 ? RegisterOperand::cast(operand)->GetRegister().code()
165 : DoubleRegisterOperand::cast(operand)
166 ->GetDoubleRegister()
167 .code();
168 *register_code = assigned_register;
149 return true; 169 return true;
150 } 170 }
151 case UsePositionHintType::kPhi: { 171 case UsePositionHintType::kPhi: {
152 auto phi = reinterpret_cast<RegisterAllocationData::PhiMapValue*>(hint_); 172 auto phi = reinterpret_cast<RegisterAllocationData::PhiMapValue*>(hint_);
153 int assigned_register = phi->assigned_register(); 173 int assigned_register = phi->assigned_register();
154 if (assigned_register == kUnassignedRegister) return false; 174 if (assigned_register == kUnassignedRegister) return false;
155 *register_index = assigned_register; 175 *register_code = assigned_register;
156 return true; 176 return true;
157 } 177 }
158 } 178 }
159 UNREACHABLE(); 179 UNREACHABLE();
160 return false; 180 return false;
161 } 181 }
162 182
163 183
164 UsePositionHintType UsePosition::HintTypeForOperand( 184 UsePositionHintType UsePosition::HintTypeForOperand(
165 const InstructionOperand& op) { 185 const InstructionOperand& op) {
(...skipping 1039 matching lines...) Expand 10 before | Expand all | Expand 10 after
1205 1225
1206 RegisterAllocationData::RegisterAllocationData( 1226 RegisterAllocationData::RegisterAllocationData(
1207 const RegisterConfiguration* config, Zone* zone, Frame* frame, 1227 const RegisterConfiguration* config, Zone* zone, Frame* frame,
1208 InstructionSequence* code, const char* debug_name) 1228 InstructionSequence* code, const char* debug_name)
1209 : allocation_zone_(zone), 1229 : allocation_zone_(zone),
1210 frame_(frame), 1230 frame_(frame),
1211 code_(code), 1231 code_(code),
1212 debug_name_(debug_name), 1232 debug_name_(debug_name),
1213 config_(config), 1233 config_(config),
1214 phi_map_(allocation_zone()), 1234 phi_map_(allocation_zone()),
1235 allocatable_codes_(this->config()->num_general_registers(), -1,
1236 allocation_zone()),
1237 allocatable_double_codes_(this->config()->num_double_registers(), -1,
1238 allocation_zone()),
1215 live_in_sets_(code->InstructionBlockCount(), nullptr, allocation_zone()), 1239 live_in_sets_(code->InstructionBlockCount(), nullptr, allocation_zone()),
1216 live_out_sets_(code->InstructionBlockCount(), nullptr, allocation_zone()), 1240 live_out_sets_(code->InstructionBlockCount(), nullptr, allocation_zone()),
1217 live_ranges_(code->VirtualRegisterCount() * 2, nullptr, 1241 live_ranges_(code->VirtualRegisterCount() * 2, nullptr,
1218 allocation_zone()), 1242 allocation_zone()),
1219 fixed_live_ranges_(this->config()->num_general_registers(), nullptr, 1243 fixed_live_ranges_(this->config()->num_general_registers(), nullptr,
1220 allocation_zone()), 1244 allocation_zone()),
1221 fixed_double_live_ranges_(this->config()->num_double_registers(), nullptr, 1245 fixed_double_live_ranges_(this->config()->num_double_registers(), nullptr,
1222 allocation_zone()), 1246 allocation_zone()),
1223 spill_ranges_(code->VirtualRegisterCount(), nullptr, allocation_zone()), 1247 spill_ranges_(code->VirtualRegisterCount(), nullptr, allocation_zone()),
1224 delayed_references_(allocation_zone()), 1248 delayed_references_(allocation_zone()),
1225 assigned_registers_(nullptr), 1249 assigned_registers_(nullptr),
1226 assigned_double_registers_(nullptr), 1250 assigned_double_registers_(nullptr),
1227 virtual_register_count_(code->VirtualRegisterCount()) { 1251 virtual_register_count_(code->VirtualRegisterCount()) {
1228 DCHECK(this->config()->num_general_registers() <= 1252 DCHECK(this->config()->num_general_registers() <=
1229 RegisterConfiguration::kMaxGeneralRegisters); 1253 RegisterConfiguration::kMaxGeneralRegisters);
1230 DCHECK(this->config()->num_double_registers() <= 1254 DCHECK(this->config()->num_double_registers() <=
1231 RegisterConfiguration::kMaxDoubleRegisters); 1255 RegisterConfiguration::kMaxDoubleRegisters);
1232 assigned_registers_ = new (code_zone()) 1256 assigned_registers_ = new (code_zone())
1233 BitVector(this->config()->num_general_registers(), code_zone()); 1257 BitVector(this->config()->num_general_registers(), code_zone());
1234 assigned_double_registers_ = new (code_zone()) 1258 assigned_double_registers_ = new (code_zone())
1235 BitVector(this->config()->num_aliased_double_registers(), code_zone()); 1259 BitVector(this->config()->num_double_registers(), code_zone());
1236 this->frame()->SetAllocatedRegisters(assigned_registers_); 1260 this->frame()->SetAllocatedRegisters(assigned_registers_);
1237 this->frame()->SetAllocatedDoubleRegisters(assigned_double_registers_); 1261 this->frame()->SetAllocatedDoubleRegisters(assigned_double_registers_);
1238 } 1262 }
1239 1263
1240 1264
1241 MoveOperands* RegisterAllocationData::AddGapMove( 1265 MoveOperands* RegisterAllocationData::AddGapMove(
1242 int index, Instruction::GapPosition position, 1266 int index, Instruction::GapPosition position,
1243 const InstructionOperand& from, const InstructionOperand& to) { 1267 const InstructionOperand& from, const InstructionOperand& to) {
1244 auto instr = code()->InstructionAt(index); 1268 auto instr = code()->InstructionAt(index);
1245 auto moves = instr->GetOrCreateParallelMove(position, code_zone()); 1269 auto moves = instr->GetOrCreateParallelMove(position, code_zone());
(...skipping 518 matching lines...) Expand 10 before | Expand all | Expand 10 after
1764 DCHECK(result->IsFixed()); 1788 DCHECK(result->IsFixed());
1765 result->set_assigned_register(index); 1789 result->set_assigned_register(index);
1766 data()->MarkAllocated(GENERAL_REGISTERS, index); 1790 data()->MarkAllocated(GENERAL_REGISTERS, index);
1767 data()->fixed_live_ranges()[index] = result; 1791 data()->fixed_live_ranges()[index] = result;
1768 } 1792 }
1769 return result; 1793 return result;
1770 } 1794 }
1771 1795
1772 1796
1773 TopLevelLiveRange* LiveRangeBuilder::FixedDoubleLiveRangeFor(int index) { 1797 TopLevelLiveRange* LiveRangeBuilder::FixedDoubleLiveRangeFor(int index) {
1774 DCHECK(index < config()->num_aliased_double_registers()); 1798 DCHECK(index < config()->num_double_registers());
1775 auto result = data()->fixed_double_live_ranges()[index]; 1799 auto result = data()->fixed_double_live_ranges()[index];
1776 if (result == nullptr) { 1800 if (result == nullptr) {
1777 result = data()->NewLiveRange(FixedDoubleLiveRangeID(index), kRepFloat64); 1801 result = data()->NewLiveRange(FixedDoubleLiveRangeID(index), kRepFloat64);
1778 DCHECK(result->IsFixed()); 1802 DCHECK(result->IsFixed());
1779 result->set_assigned_register(index); 1803 result->set_assigned_register(index);
1780 data()->MarkAllocated(DOUBLE_REGISTERS, index); 1804 data()->MarkAllocated(DOUBLE_REGISTERS, index);
1781 data()->fixed_double_live_ranges()[index] = result; 1805 data()->fixed_double_live_ranges()[index] = result;
1782 } 1806 }
1783 return result; 1807 return result;
1784 } 1808 }
1785 1809
1786 1810
1787 TopLevelLiveRange* LiveRangeBuilder::LiveRangeFor(InstructionOperand* operand) { 1811 TopLevelLiveRange* LiveRangeBuilder::LiveRangeFor(InstructionOperand* operand) {
1788 if (operand->IsUnallocated()) { 1812 if (operand->IsUnallocated()) {
1789 return data()->GetOrCreateLiveRangeFor( 1813 return data()->GetOrCreateLiveRangeFor(
1790 UnallocatedOperand::cast(operand)->virtual_register()); 1814 UnallocatedOperand::cast(operand)->virtual_register());
1791 } else if (operand->IsConstant()) { 1815 } else if (operand->IsConstant()) {
1792 return data()->GetOrCreateLiveRangeFor( 1816 return data()->GetOrCreateLiveRangeFor(
1793 ConstantOperand::cast(operand)->virtual_register()); 1817 ConstantOperand::cast(operand)->virtual_register());
1794 } else if (operand->IsRegister()) { 1818 } else if (operand->IsRegister()) {
1795 return FixedLiveRangeFor(RegisterOperand::cast(operand)->index()); 1819 return FixedLiveRangeFor(
1820 RegisterOperand::cast(operand)->GetRegister().code());
1796 } else if (operand->IsDoubleRegister()) { 1821 } else if (operand->IsDoubleRegister()) {
1797 return FixedDoubleLiveRangeFor( 1822 return FixedDoubleLiveRangeFor(
1798 DoubleRegisterOperand::cast(operand)->index()); 1823 DoubleRegisterOperand::cast(operand)->GetDoubleRegister().code());
1799 } else { 1824 } else {
1800 return nullptr; 1825 return nullptr;
1801 } 1826 }
1802 } 1827 }
1803 1828
1804 1829
1805 UsePosition* LiveRangeBuilder::NewUsePosition(LifetimePosition pos, 1830 UsePosition* LiveRangeBuilder::NewUsePosition(LifetimePosition pos,
1806 InstructionOperand* operand, 1831 InstructionOperand* operand,
1807 void* hint, 1832 void* hint,
1808 UsePositionHintType hint_type) { 1833 UsePositionHintType hint_type) {
(...skipping 69 matching lines...) Expand 10 before | Expand all | Expand 10 after
1878 // exception value. 1903 // exception value.
1879 // TODO(mtrofin): should we explore an explicit opcode for 1904 // TODO(mtrofin): should we explore an explicit opcode for
1880 // the first instruction in the handler? 1905 // the first instruction in the handler?
1881 Define(LifetimePosition::GapFromInstructionIndex(index), output); 1906 Define(LifetimePosition::GapFromInstructionIndex(index), output);
1882 } else { 1907 } else {
1883 Define(curr_position, output); 1908 Define(curr_position, output);
1884 } 1909 }
1885 } 1910 }
1886 1911
1887 if (instr->ClobbersRegisters()) { 1912 if (instr->ClobbersRegisters()) {
1888 for (int i = 0; i < config()->num_general_registers(); ++i) { 1913 for (int i = 0; i < config()->num_allocatable_general_registers(); ++i) {
1889 if (!IsOutputRegisterOf(instr, i)) { 1914 int code = config()->GetAllocatableGeneralCode(i);
1890 auto range = FixedLiveRangeFor(i); 1915 if (!IsOutputRegisterOf(instr, Register::from_code(code))) {
1916 auto range = FixedLiveRangeFor(code);
1891 range->AddUseInterval(curr_position, curr_position.End(), 1917 range->AddUseInterval(curr_position, curr_position.End(),
1892 allocation_zone()); 1918 allocation_zone());
1893 } 1919 }
1894 } 1920 }
1895 } 1921 }
1896 1922
1897 if (instr->ClobbersDoubleRegisters()) { 1923 if (instr->ClobbersDoubleRegisters()) {
1898 for (int i = 0; i < config()->num_aliased_double_registers(); ++i) { 1924 for (int i = 0; i < config()->num_allocatable_aliased_double_registers();
1899 if (!IsOutputDoubleRegisterOf(instr, i)) { 1925 ++i) {
1900 auto range = FixedDoubleLiveRangeFor(i); 1926 int code = config()->GetAllocatableDoubleCode(i);
1927 if (!IsOutputDoubleRegisterOf(instr, DoubleRegister::from_code(code))) {
1928 auto range = FixedDoubleLiveRangeFor(code);
1901 range->AddUseInterval(curr_position, curr_position.End(), 1929 range->AddUseInterval(curr_position, curr_position.End(),
1902 allocation_zone()); 1930 allocation_zone());
1903 } 1931 }
1904 } 1932 }
1905 } 1933 }
1906 1934
1907 for (size_t i = 0; i < instr->InputCount(); i++) { 1935 for (size_t i = 0; i < instr->InputCount(); i++) {
1908 auto input = instr->InputAt(i); 1936 auto input = instr->InputAt(i);
1909 if (input->IsImmediate()) continue; // Ignore immediates. 1937 if (input->IsImmediate()) continue; // Ignore immediates.
1910 LifetimePosition use_pos; 1938 LifetimePosition use_pos;
(...skipping 225 matching lines...) Expand 10 before | Expand all | Expand 10 after
2136 for (LiveRange* current : data()->live_ranges()) { 2164 for (LiveRange* current : data()->live_ranges()) {
2137 if (current != nullptr) current->Verify(); 2165 if (current != nullptr) current->Verify();
2138 } 2166 }
2139 } 2167 }
2140 2168
2141 2169
2142 RegisterAllocator::RegisterAllocator(RegisterAllocationData* data, 2170 RegisterAllocator::RegisterAllocator(RegisterAllocationData* data,
2143 RegisterKind kind) 2171 RegisterKind kind)
2144 : data_(data), 2172 : data_(data),
2145 mode_(kind), 2173 mode_(kind),
2146 num_registers_(GetRegisterCount(data->config(), kind)) {} 2174 num_registers_(GetRegisterCount(data->config(), kind)),
2175 num_allocatable_registers_(
2176 GetAllocatableRegisterCount(data->config(), kind)),
2177 allocatable_register_codes_(
2178 GetAllocatableRegisterCodes(data->config(), kind)) {}
2147 2179
2148 2180
2149 LiveRange* RegisterAllocator::SplitRangeAt(LiveRange* range, 2181 LiveRange* RegisterAllocator::SplitRangeAt(LiveRange* range,
2150 LifetimePosition pos) { 2182 LifetimePosition pos) {
2151 DCHECK(!range->TopLevel()->IsFixed()); 2183 DCHECK(!range->TopLevel()->IsFixed());
2152 TRACE("Splitting live range %d:%d at %d\n", range->TopLevel()->vreg(), 2184 TRACE("Splitting live range %d:%d at %d\n", range->TopLevel()->vreg(),
2153 range->relative_id(), pos.value()); 2185 range->relative_id(), pos.value());
2154 2186
2155 if (pos <= range->Start()) return range; 2187 if (pos <= range->Start()) return range;
2156 2188
(...skipping 102 matching lines...) Expand 10 before | Expand all | Expand 10 after
2259 } 2291 }
2260 2292
2261 2293
2262 const ZoneVector<TopLevelLiveRange*>& RegisterAllocator::GetFixedRegisters() 2294 const ZoneVector<TopLevelLiveRange*>& RegisterAllocator::GetFixedRegisters()
2263 const { 2295 const {
2264 return mode() == DOUBLE_REGISTERS ? data()->fixed_double_live_ranges() 2296 return mode() == DOUBLE_REGISTERS ? data()->fixed_double_live_ranges()
2265 : data()->fixed_live_ranges(); 2297 : data()->fixed_live_ranges();
2266 } 2298 }
2267 2299
2268 2300
2269 const char* RegisterAllocator::RegisterName(int allocation_index) const { 2301 const char* RegisterAllocator::RegisterName(int register_code) const {
2270 if (mode() == GENERAL_REGISTERS) { 2302 if (mode() == GENERAL_REGISTERS) {
2271 return data()->config()->general_register_name(allocation_index); 2303 return data()->config()->GetGeneralRegisterName(register_code);
2272 } else { 2304 } else {
2273 return data()->config()->double_register_name(allocation_index); 2305 return data()->config()->GetDoubleRegisterName(register_code);
2274 } 2306 }
2275 } 2307 }
2276 2308
2277 2309
2278 LinearScanAllocator::LinearScanAllocator(RegisterAllocationData* data, 2310 LinearScanAllocator::LinearScanAllocator(RegisterAllocationData* data,
2279 RegisterKind kind, Zone* local_zone) 2311 RegisterKind kind, Zone* local_zone)
2280 : RegisterAllocator(data, kind), 2312 : RegisterAllocator(data, kind),
2281 unhandled_live_ranges_(local_zone), 2313 unhandled_live_ranges_(local_zone),
2282 active_live_ranges_(local_zone), 2314 active_live_ranges_(local_zone),
2283 inactive_live_ranges_(local_zone) { 2315 inactive_live_ranges_(local_zone) {
(...skipping 218 matching lines...) Expand 10 before | Expand all | Expand 10 after
2502 bool LinearScanAllocator::TryAllocateFreeReg(LiveRange* current) { 2534 bool LinearScanAllocator::TryAllocateFreeReg(LiveRange* current) {
2503 LifetimePosition free_until_pos[RegisterConfiguration::kMaxDoubleRegisters]; 2535 LifetimePosition free_until_pos[RegisterConfiguration::kMaxDoubleRegisters];
2504 2536
2505 for (int i = 0; i < num_registers(); i++) { 2537 for (int i = 0; i < num_registers(); i++) {
2506 free_until_pos[i] = LifetimePosition::MaxPosition(); 2538 free_until_pos[i] = LifetimePosition::MaxPosition();
2507 } 2539 }
2508 2540
2509 for (auto cur_active : active_live_ranges()) { 2541 for (auto cur_active : active_live_ranges()) {
2510 free_until_pos[cur_active->assigned_register()] = 2542 free_until_pos[cur_active->assigned_register()] =
2511 LifetimePosition::GapFromInstructionIndex(0); 2543 LifetimePosition::GapFromInstructionIndex(0);
2544 TRACE("Register %s is free until pos %d (1)\n",
2545 RegisterName(cur_active->assigned_register()),
2546 LifetimePosition::GapFromInstructionIndex(0).value());
2512 } 2547 }
2513 2548
2514 for (auto cur_inactive : inactive_live_ranges()) { 2549 for (auto cur_inactive : inactive_live_ranges()) {
2515 DCHECK(cur_inactive->End() > current->Start()); 2550 DCHECK(cur_inactive->End() > current->Start());
2516 auto next_intersection = cur_inactive->FirstIntersection(current); 2551 auto next_intersection = cur_inactive->FirstIntersection(current);
2517 if (!next_intersection.IsValid()) continue; 2552 if (!next_intersection.IsValid()) continue;
2518 int cur_reg = cur_inactive->assigned_register(); 2553 int cur_reg = cur_inactive->assigned_register();
2519 free_until_pos[cur_reg] = Min(free_until_pos[cur_reg], next_intersection); 2554 free_until_pos[cur_reg] = Min(free_until_pos[cur_reg], next_intersection);
2555 TRACE("Register %s is free until pos %d (2)\n", RegisterName(cur_reg),
2556 Min(free_until_pos[cur_reg], next_intersection).value());
2520 } 2557 }
2521 2558
2522 int hint_register; 2559 int hint_register;
2523 if (current->FirstHintPosition(&hint_register) != nullptr) { 2560 if (current->FirstHintPosition(&hint_register) != nullptr) {
2524 TRACE( 2561 TRACE(
2525 "Found reg hint %s (free until [%d) for live range %d:%d (end %d[).\n", 2562 "Found reg hint %s (free until [%d) for live range %d:%d (end %d[).\n",
2526 RegisterName(hint_register), free_until_pos[hint_register].value(), 2563 RegisterName(hint_register), free_until_pos[hint_register].value(),
2527 current->TopLevel()->vreg(), current->relative_id(), 2564 current->TopLevel()->vreg(), current->relative_id(),
2528 current->End().value()); 2565 current->End().value());
2529 2566
2530 // The desired register is free until the end of the current live range. 2567 // The desired register is free until the end of the current live range.
2531 if (free_until_pos[hint_register] >= current->End()) { 2568 if (free_until_pos[hint_register] >= current->End()) {
2532 TRACE("Assigning preferred reg %s to live range %d:%d\n", 2569 TRACE("Assigning preferred reg %s to live range %d:%d\n",
2533 RegisterName(hint_register), current->TopLevel()->vreg(), 2570 RegisterName(hint_register), current->TopLevel()->vreg(),
2534 current->relative_id()); 2571 current->relative_id());
2535 SetLiveRangeAssignedRegister(current, hint_register); 2572 SetLiveRangeAssignedRegister(current, hint_register);
2536 return true; 2573 return true;
2537 } 2574 }
2538 } 2575 }
2539 2576
2540 // Find the register which stays free for the longest time. 2577 // Find the register which stays free for the longest time.
2541 int reg = 0; 2578 int reg = allocatable_register_code(0);
2542 for (int i = 1; i < num_registers(); ++i) { 2579 for (int i = 1; i < num_alloctable_registers(); ++i) {
2543 if (free_until_pos[i] > free_until_pos[reg]) { 2580 int code = allocatable_register_code(i);
2544 reg = i; 2581 if (free_until_pos[code] > free_until_pos[reg]) {
2582 reg = code;
2545 } 2583 }
2546 } 2584 }
2547 2585
2548 auto pos = free_until_pos[reg]; 2586 auto pos = free_until_pos[reg];
2549 2587
2550 if (pos <= current->Start()) { 2588 if (pos <= current->Start()) {
2551 // All registers are blocked. 2589 // All registers are blocked.
2552 return false; 2590 return false;
2553 } 2591 }
2554 2592
(...skipping 54 matching lines...) Expand 10 before | Expand all | Expand 10 after
2609 if (!next_intersection.IsValid()) continue; 2647 if (!next_intersection.IsValid()) continue;
2610 int cur_reg = range->assigned_register(); 2648 int cur_reg = range->assigned_register();
2611 if (range->TopLevel()->IsFixed()) { 2649 if (range->TopLevel()->IsFixed()) {
2612 block_pos[cur_reg] = Min(block_pos[cur_reg], next_intersection); 2650 block_pos[cur_reg] = Min(block_pos[cur_reg], next_intersection);
2613 use_pos[cur_reg] = Min(block_pos[cur_reg], use_pos[cur_reg]); 2651 use_pos[cur_reg] = Min(block_pos[cur_reg], use_pos[cur_reg]);
2614 } else { 2652 } else {
2615 use_pos[cur_reg] = Min(use_pos[cur_reg], next_intersection); 2653 use_pos[cur_reg] = Min(use_pos[cur_reg], next_intersection);
2616 } 2654 }
2617 } 2655 }
2618 2656
2619 int reg = 0; 2657 int reg = allocatable_register_code(0);
2620 for (int i = 1; i < num_registers(); ++i) { 2658 for (int i = 1; i < num_alloctable_registers(); ++i) {
2621 if (use_pos[i] > use_pos[reg]) { 2659 int code = allocatable_register_code(i);
2622 reg = i; 2660 if (use_pos[code] > use_pos[reg]) {
2661 reg = code;
2623 } 2662 }
2624 } 2663 }
2625 2664
2626 auto pos = use_pos[reg]; 2665 auto pos = use_pos[reg];
2627 2666
2628 if (pos < register_use->pos()) { 2667 if (pos < register_use->pos()) {
2629 // All registers are blocked before the first use that requires a register. 2668 // All registers are blocked before the first use that requires a register.
2630 // Spill starting part of live range up to that use. 2669 // Spill starting part of live range up to that use.
2631 SpillBetween(current, current->Start(), register_use->pos()); 2670 SpillBetween(current, current->Start(), register_use->pos());
2632 return; 2671 return;
(...skipping 686 matching lines...) Expand 10 before | Expand all | Expand 10 after
3319 auto eliminate = moves->PrepareInsertAfter(move); 3358 auto eliminate = moves->PrepareInsertAfter(move);
3320 to_insert.push_back(move); 3359 to_insert.push_back(move);
3321 if (eliminate != nullptr) to_eliminate.push_back(eliminate); 3360 if (eliminate != nullptr) to_eliminate.push_back(eliminate);
3322 } 3361 }
3323 } 3362 }
3324 3363
3325 3364
3326 } // namespace compiler 3365 } // namespace compiler
3327 } // namespace internal 3366 } // namespace internal
3328 } // namespace v8 3367 } // namespace v8
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