Make FlushICache NOP for Nvidia Denver 1.0 only

src/arm64/assembler-arm64.cc

Index: src/arm64/assembler-arm64.cc
diff --git a/src/arm64/assembler-arm64.cc b/src/arm64/assembler-arm64.cc
index 8db7126fcf44c3be8c93d4453e3cece753a1eca8..235b5ee2bcaa96078ceddbb4f543133a4b040781 100644
--- a/src/arm64/assembler-arm64.cc
+++ b/src/arm64/assembler-arm64.cc
@@ -52,7 +52,8 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
   // Probe for runtime features
   base::CPU cpu;
   if (cpu.implementer() == base::CPU::NVIDIA &&
-      cpu.variant() == base::CPU::NVIDIA_DENVER) {
+      cpu.variant() == base::CPU::NVIDIA_DENVER &&

[Rodolph Perfetta (ARM), 2015/08/19 08:19:27]

Denver is a CPU part (like A57, A53 for ARM), so it looks like the checks are
switched: part should be Denver and variant should be less than 0, 1 or 2. no?
The initial code was wrong then.

[avanbrunt, 2015/08/19 16:35:38]

Implementer == 'N' and and variant == 0x0 combined identify the Denver family.
The different implementations are distinguished by the primary part number. Part
number 0x000, 0x001, and 0x002 all have a coherent instruction cache.

+      cpu.part() <= base::CPU::NVIDIA_DENVER_V10) {
     supported_ |= 1u << COHERENT_CACHE;
   }
 }