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| 1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// | 1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 3615 // TODO(ascull): if the count is constant but val is not it would be possible | 3615 // TODO(ascull): if the count is constant but val is not it would be possible |
| 3616 // to inline by spreading the value across 4 bytes and accessing subregs e.g. | 3616 // to inline by spreading the value across 4 bytes and accessing subregs e.g. |
| 3617 // eax, ax and al. | 3617 // eax, ax and al. |
| 3618 if (IsCountConst && IsValConst) { | 3618 if (IsCountConst && IsValConst) { |
| 3619 Variable *Base = nullptr; | 3619 Variable *Base = nullptr; |
| 3620 const uint32_t SpreadValue = | 3620 const uint32_t SpreadValue = |
| 3621 (ValValue << 24) | (ValValue << 16) | (ValValue << 8) | ValValue; | 3621 (ValValue << 24) | (ValValue << 16) | (ValValue << 8) | ValValue; |
| 3622 Variable *VecReg = nullptr; | 3622 Variable *VecReg = nullptr; |
| 3623 | 3623 |
| 3624 auto lowerSet = [this, &Base, SpreadValue, &VecReg](Type Ty, | 3624 auto lowerSet = [this, &Base, SpreadValue, &VecReg](Type Ty, |
| 3625 uint32_t OffsetAmt) { | 3625 uint32_t OffsetAmt) { |
| 3626 assert(Base != nullptr); | 3626 assert(Base != nullptr); |
| 3627 Constant *Offset = OffsetAmt ? Ctx->getConstantInt32(OffsetAmt) : nullptr; | 3627 Constant *Offset = OffsetAmt ? Ctx->getConstantInt32(OffsetAmt) : nullptr; |
| 3628 | 3628 |
| 3629 // TODO(ascull): is 64-bit better with vector or scalar movq? | 3629 // TODO(ascull): is 64-bit better with vector or scalar movq? |
| 3630 auto *Mem = Traits::X86OperandMem::create(Func, Ty, Base, Offset); | 3630 auto *Mem = Traits::X86OperandMem::create(Func, Ty, Base, Offset); |
| 3631 if (isVectorType(Ty)) { | 3631 if (isVectorType(Ty)) { |
| 3632 assert(VecReg != nullptr); | 3632 assert(VecReg != nullptr); |
| 3633 _storep(VecReg, Mem); | 3633 _storep(VecReg, Mem); |
| 3634 } else if (Ty == IceType_i64) { | 3634 } else if (Ty == IceType_i64) { |
| 3635 assert(VecReg != nullptr); | 3635 assert(VecReg != nullptr); |
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| 5162 } | 5162 } |
| 5163 // the offset is not eligible for blinding or pooling, return the original | 5163 // the offset is not eligible for blinding or pooling, return the original |
| 5164 // mem operand | 5164 // mem operand |
| 5165 return MemOperand; | 5165 return MemOperand; |
| 5166 } | 5166 } |
| 5167 | 5167 |
| 5168 } // end of namespace X86Internal | 5168 } // end of namespace X86Internal |
| 5169 } // end of namespace Ice | 5169 } // end of namespace Ice |
| 5170 | 5170 |
| 5171 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H | 5171 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H |
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