Adds MIPS SPECIAL instructions to simulator, assembler, debugger.

runtime/vm/assembler_mips.h

Index: runtime/vm/assembler_mips.h
===================================================================
--- runtime/vm/assembler_mips.h	(revision 20092)
+++ runtime/vm/assembler_mips.h	(working copy)
@@ -224,7 +224,7 @@
     return this;
   }
 
-  // CPU instructions.
+  // CPU instructions in alphabetical order.
   void addiu(Register rt, Register rs, const Immediate& imm) {
     ASSERT(Utils::IsInt(16, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
@@ -268,7 +268,19 @@
     EmitRType(SPECIAL, rs, rt, R0, 0, DIVU);
   }
 
+  void jalr(Register rs, Register rd) {

[Ivan Posva, 2013/03/21 00:08:06]

If you do this:
void jalr(Register rs, Register rd = RA)

Then you can have your cake and eat it too.

[zra, 2013/03/21 15:49:08]

Done.

+    ASSERT(rs != rd);
+    ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.
+    EmitRType(SPECIAL, rs, R0, rd, 0, JALR);
+    EmitBranchDelayNop();
+  }
 
+  void jr(Register rs) {
+    ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.
+    EmitRType(SPECIAL, rs, R0, R0, 0, JR);
+    EmitBranchDelayNop();
+  }
+
   void lb(Register rt, const Address& addr) {
     EmitLoadStore(LB, rt, addr);
   }
@@ -303,19 +315,36 @@
     EmitRType(SPECIAL, R0, R0, rd, 0, MFLO);
   }
 
+  void movn(Register rd, Register rs, Register rt) {
+    EmitRType(SPECIAL, rs, rt, rd, 0, MOVN);
+  }
+
+  void movz(Register rd, Register rs, Register rt) {
+    EmitRType(SPECIAL, rs, rt, rd, 0, MOVZ);
+  }
+
+  void mult(Register rs, Register rt) {
+    EmitRType(SPECIAL, rs, rt, R0, 0, MULT);
+  }
+
+  void multu(Register rs, Register rt) {
+    EmitRType(SPECIAL, rs, rt, R0, 0, MULTU);
+  }
+
+  void nor(Register rd, Register rs, Register rt) {
+    EmitRType(SPECIAL, rs, rt, rd, 0, NOR);
+  }
+
+  void or_(Register rd, Register rs, Register rt) {
+    EmitRType(SPECIAL, rs, rt, rd, 0, OR);
+  }
+
   void ori(Register rt, Register rs, const Immediate& imm) {
     ASSERT(Utils::IsUint(16, imm.value()));
     uint16_t imm_value = static_cast<uint16_t>(imm.value());
     EmitIType(ORI, rs, rt, imm_value);
   }
 
-  void jr(Register rs) {
-    ASSERT(!in_delay_slot_);  // Jump within a delay slot is not supported.
-    EmitRType(SPECIAL, rs, R0, R0, 0, JR);
-    Emit(Instr::kNopInstruction);  // Branch delay NOP.
-    delay_slot_available_ = true;
-  }
-
   void sb(Register rt, const Address& addr) {
     EmitLoadStore(SB, rt, addr);
   }
@@ -324,20 +353,73 @@
     EmitLoadStore(SH, rt, addr);
   }
 
+  void sll(Register rd, Register rt, int sa) {
+    EmitRType(SPECIAL, R0, rt, rd, sa, SLL);
+  }
+
+  void sllv(Register rd, Register rt, Register rs) {
+    EmitRType(SPECIAL, rs, rt, rd, 0, SLLV);
+  }
+
+  void slt(Register rd, Register rs, Register rt) {
+    EmitRType(SPECIAL, rs, rt, rd, 0, SLT);
+  }
+
+  void sltu(Register rd, Register rs, Register rt) {
+    EmitRType(SPECIAL, rs, rt, rd, 0, SLTU);
+  }
+
+  void sra(Register rd, Register rt, int sa) {
+    EmitRType(SPECIAL, R0, rt, rd, sa, SRA);
+  }
+
+  void srav(Register rd, Register rt, Register rs) {
+    EmitRType(SPECIAL, rs, rt, rd, 0, SRAV);
+  }
+
+  void srl(Register rd, Register rt, int sa) {
+    EmitRType(SPECIAL, R0, rt, rd, sa, SRL);
+  }
+
+  void srlv(Register rd, Register rt, Register rs) {
+    EmitRType(SPECIAL, rs, rt, rd, 0, SRLV);
+  }
+
+  void sub(Register rd, Register rs, Register rt) {
+    EmitRType(SPECIAL, rs, rt, rd, 0, SUB);
+  }
+
+  void subu(Register rd, Register rs, Register rt) {
+    EmitRType(SPECIAL, rs, rt, rd, 0, SUBU);
+  }
+
   void sw(Register rt, const Address& addr) {
     EmitLoadStore(SW, rt, addr);
   }
 
-  void sll(Register rd, Register rt, int sa) {
-    EmitRType(SPECIAL, R0, rt, rd, sa, SLL);
+  void xor_(Register rd, Register rs, Register rt) {
+    EmitRType(SPECIAL, rs, rt, rd, 0, XOR);
   }
 
-  // Macros.
+  // Macros in alphabetical order.
   void LoadImmediate(Register rd, int32_t value) {
-    lui(rd, Immediate((value >> 16) & 0xffff));
-    ori(rd, rd, Immediate(value & 0xffff));
+    if (Utils::IsInt(16, value)) {
+      addiu(rd, ZR, Immediate(value));
+    } else {
+      lui(rd, Immediate((value >> 16) & 0xffff));
+      ori(rd, rd, Immediate(value & 0xffff));
+    }
   }
 
+  void Move(Register rd, Register rs) {
+    or_(rd, rs, ZR);
+  }
+
+  void EmitBranchDelayNop() {

[Ivan Posva, 2013/03/21 00:08:06]

I expect this to be private:.

[zra, 2013/03/21 15:49:08]

Done.

+    Emit(Instr::kNopInstruction);  // Branch delay NOP.
+    delay_slot_available_ = true;
+  }
+
  private:
   AssemblerBuffer buffer_;
   GrowableObjectArray& object_pool_;  // Objects and patchable jump targets.