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Side by Side Diff: runtime/vm/disassembler_mips.cc

Issue 12837009: Adds MIPS SPECIAL instructions to simulator, assembler, debugger. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 9 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/disassembler.h" 5 #include "vm/disassembler.h"
6 6
7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_MIPS. 7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_MIPS.
8 #if defined(TARGET_ARCH_MIPS) 8 #if defined(TARGET_ARCH_MIPS)
9 #include "platform/assert.h" 9 #include "platform/assert.h"
10 10
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222 break; 222 break;
223 } 223 }
224 case DIV: { 224 case DIV: {
225 Format(instr, "div 'rs, 'rt"); 225 Format(instr, "div 'rs, 'rt");
226 break; 226 break;
227 } 227 }
228 case DIVU: { 228 case DIVU: {
229 Format(instr, "divu 'rs, 'rt"); 229 Format(instr, "divu 'rs, 'rt");
230 break; 230 break;
231 } 231 }
232 case JALR: {
233 Format(instr, "jalr'hint 'rd, 'rs");
234 break;
235 }
236 case JR: {
237 Format(instr, "jr'hint 'rs");
238 break;
239 }
232 case MFHI: { 240 case MFHI: {
233 Format(instr, "mfhi 'rd"); 241 Format(instr, "mfhi 'rd");
234 break; 242 break;
235 } 243 }
236 case MFLO: { 244 case MFLO: {
237 Format(instr, "mflo 'rd"); 245 Format(instr, "mflo 'rd");
238 break; 246 break;
239 } 247 }
248 case MOVN: {
249 Format(instr, "movn 'rd, 'rs, 'rt");
250 break;
251 }
252 case MOVZ: {
253 Format(instr, "movz 'rd, 'rs, 'rt");
254 break;
255 }
256 case MULT: {
257 Format(instr, "mult 'rs, 'rt");
258 break;
259 }
260 case MULTU: {
261 Format(instr, "multu 'rs, 'rt");
262 break;
263 }
264 case NOR: {
265 Format(instr, "nor 'rd, 'rs, 'rt");
266 break;
267 }
268 case OR: {
269 if (instr->RsField() == 0 && instr->RtField() == 0) {
270 Format(instr, "mov 'rd, 0");
271 } else if (instr->RsField() == R0) {
272 Format(instr, "mov 'rd, 'rt");
273 } else if (instr->RtField() == R0) {
274 Format(instr, "mov 'rd, 'rs");
275 } else {
276 Format(instr, "or 'rd, 'rs, 'rt");
277 }
278 break;
279 }
240 case SLL: { 280 case SLL: {
241 if ((instr->RdField() == R0) && 281 if ((instr->RdField() == R0) &&
242 (instr->RtField() == R0) && 282 (instr->RtField() == R0) &&
243 (instr->SaField() == 0)) { 283 (instr->SaField() == 0)) {
244 Format(instr, "nop"); 284 Format(instr, "nop");
245 } else { 285 } else {
246 Format(instr, "sll 'rd, 'rt, 'sa"); 286 Format(instr, "sll 'rd, 'rt, 'sa");
247 } 287 }
248 break; 288 break;
249 } 289 }
250 case JR: { 290 case SLLV: {
251 Format(instr, "jr'hint 'rs"); 291 Format(instr, "sllv 'rd, 'rt, 'rs");
292 break;
293 }
294 case SLT: {
295 Format(instr, "slt 'rd, 'rs, 'rt");
296 break;
297 }
298 case SLTU: {
299 Format(instr, "sltu 'rd, 'rs, 'rt");
300 break;
301 }
302 case SRA: {
303 if (instr->RsField() == 0) {
304 Format(instr, "sra 'rd, 'rt, 'sa");
305 } else {
306 Unknown(instr);
307 }
308 break;
309 }
310 case SRAV: {
311 Format(instr, "srav 'rd, 'rt, 'rs");
312 break;
313 }
314 case SRL: {
315 if (instr->RsField() == 0) {
316 Format(instr, "srl 'rd, 'rt, 'sa");
317 } else {
318 Unknown(instr);
319 }
320 break;
321 }
322 case SRLV: {
323 if (instr->SaField() == 0) {
324 Format(instr, "srlv 'rd, 'rt, 'rs");
325 } else {
326 Unknown(instr);
327 }
328 break;
329 }
330 case SUB: {
331 Format(instr, "sub 'rd, 'rs, 'rt");
332 break;
333 }
334 case SUBU: {
335 Format(instr, "subu 'rd, 'rs, 'rt");
336 break;
337 }
338 case XOR: {
339 Format(instr, "xor 'rd, 'rs, 'rt");
252 break; 340 break;
253 } 341 }
254 default: { 342 default: {
255 Unknown(instr); 343 Unknown(instr);
256 break; 344 break;
257 } 345 }
258 } 346 }
259 } 347 }
260 348
261 349
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387 pc); 475 pc);
388 pc += instruction_length; 476 pc += instruction_length;
389 } 477 }
390 478
391 return success; 479 return success;
392 } 480 }
393 481
394 } // namespace dart 482 } // namespace dart
395 483
396 #endif // defined TARGET_ARCH_MIPS 484 #endif // defined TARGET_ARCH_MIPS
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