| Index: src/IceInstX86BaseImpl.h
|
| diff --git a/src/IceInstX86BaseImpl.h b/src/IceInstX86BaseImpl.h
|
| index 34417cf5cce95d1b3a882d2f4d7bcf19891536a4..29fc0759d3ed9b86d23156c60ea42a241a1c9c3f 100644
|
| --- a/src/IceInstX86BaseImpl.h
|
| +++ b/src/IceInstX86BaseImpl.h
|
| @@ -3143,6 +3143,21 @@ void InstX86Xchg<Machine>::emitIAS(const Cfg *Func) const {
|
| typename InstX86Base<Machine>::Traits::Assembler *Asm =
|
| Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
|
| Type Ty = this->getSrc(0)->getType();
|
| + const auto VarReg1 = llvm::cast<Variable>(this->getSrc(1));
|
| + assert(VarReg1->hasReg());
|
| + const typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister Reg1 =
|
| + InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
|
| + VarReg1->getRegNum());
|
| +
|
| + if (const auto VarReg0 = llvm::dyn_cast<Variable>(this->getSrc(0))) {
|
| + assert(VarReg0->hasReg());
|
| + const typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister Reg0 =
|
| + InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
|
| + VarReg0->getRegNum());
|
| + Asm->xchg(Ty, Reg0, Reg1);
|
| + return;
|
| + }
|
| +
|
| const auto Mem =
|
| llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
|
| this->getSrc(0));
|
| @@ -3150,12 +3165,7 @@ void InstX86Xchg<Machine>::emitIAS(const Cfg *Func) const {
|
| InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
|
| const typename InstX86Base<Machine>::Traits::Address Addr =
|
| Mem->toAsmAddress(Asm);
|
| - const auto VarReg = llvm::cast<Variable>(this->getSrc(1));
|
| - assert(VarReg->hasReg());
|
| - const typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister Reg =
|
| - InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
|
| - VarReg->getRegNum());
|
| - Asm->xchg(Ty, Addr, Reg);
|
| + Asm->xchg(Ty, Addr, Reg1);
|
| }
|
|
|
| template <class Machine>
|
|
|