Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(492)

Side by Side Diff: src/IceAssemblerX86Base.h

Issue 1278173009: Inline memove for small constant sizes and refactor memcpy and memset. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: r1 == rax Created 5 years, 4 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
OLDNEW
1 //===- subzero/src/IceAssemblerX86Base.h - base x86 assembler -*- C++ -*---===// 1 //===- subzero/src/IceAssemblerX86Base.h - base x86 assembler -*- C++ -*---===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
(...skipping 812 matching lines...) Expand 10 before | Expand all | Expand 10 after
823 void jmp(const ConstantRelocatable *label); // not testable. 823 void jmp(const ConstantRelocatable *label); // not testable.
824 824
825 void mfence(); 825 void mfence();
826 826
827 void lock(); 827 void lock();
828 void cmpxchg(Type Ty, const typename Traits::Address &address, 828 void cmpxchg(Type Ty, const typename Traits::Address &address,
829 typename Traits::GPRRegister reg, bool Locked); 829 typename Traits::GPRRegister reg, bool Locked);
830 void cmpxchg8b(const typename Traits::Address &address, bool Locked); 830 void cmpxchg8b(const typename Traits::Address &address, bool Locked);
831 void xadd(Type Ty, const typename Traits::Address &address, 831 void xadd(Type Ty, const typename Traits::Address &address,
832 typename Traits::GPRRegister reg, bool Locked); 832 typename Traits::GPRRegister reg, bool Locked);
833 void xchg(Type Ty, typename Traits::GPRRegister reg0,
834 typename Traits::GPRRegister reg1);
833 void xchg(Type Ty, const typename Traits::Address &address, 835 void xchg(Type Ty, const typename Traits::Address &address,
834 typename Traits::GPRRegister reg); 836 typename Traits::GPRRegister reg);
835 837
836 /// \name Intel Architecture Code Analyzer markers. 838 /// \name Intel Architecture Code Analyzer markers.
837 /// @{ 839 /// @{
838 void iaca_start(); 840 void iaca_start();
839 void iaca_end(); 841 void iaca_end();
840 /// @} 842 /// @}
841 843
842 void emitSegmentOverride(uint8_t prefix); 844 void emitSegmentOverride(uint8_t prefix);
(...skipping 202 matching lines...) Expand 10 before | Expand all | Expand 10 after
1045 emitUint8(0x66); 1047 emitUint8(0x66);
1046 } 1048 }
1047 1049
1048 } // end of namespace X86Internal 1050 } // end of namespace X86Internal
1049 1051
1050 } // end of namespace Ice 1052 } // end of namespace Ice
1051 1053
1052 #include "IceAssemblerX86BaseImpl.h" 1054 #include "IceAssemblerX86BaseImpl.h"
1053 1055
1054 #endif // SUBZERO_SRC_ICEASSEMBLERX86BASE_H 1056 #endif // SUBZERO_SRC_ICEASSEMBLERX86BASE_H
OLDNEW

Powered by Google App Engine
This is Rietveld 408576698