Inline memove for small constant sizes and refactor memcpy and memset.

tests_lit/llvm2ice_tests/nacl-mem-intrinsics.ll

 ; This tests the NaCl intrinsics memset, memcpy and memmove.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -sandbox \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN:   --target x8632 -i %s --args -Om1 -sandbox \
+; RUN:   --target x8632 -i %s --args -Om1 --fmem-intrin-opt -sandbox \

[Jim Stichnoth, 2015/08/18 17:11:28]

I think you should have one more RUN configuration that tests Om1 without
-fmem-intrin-opt.  The CHECK lines would look pretty much like the ARM checks.

[ascull, 2015/08/18 18:38:01]

Done.

 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command %p2i --filetype=asm --assemble --disassemble --target arm32 \
 ; RUN:   -i %s --args -O2 --skip-unimplemented \
 ; RUN:   | %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command FileCheck --check-prefix ARM32 %s
 
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
 declare void @llvm.memmove.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
@@ skipping 120 matching lines @@
 ; CHECK: movups [[REG:xmm[0-9]+]],XMMWORD PTR [{{.*}}+0x10]
 ; CHECK-NEXT: movups XMMWORD PTR [{{.*}}+0x10],[[REG]]
 ; CHECK-NEXT: movups [[REG:xmm[0-9]+]],XMMWORD PTR [{{.*}}]
 ; CHECK-NEXT: movups XMMWORD PTR [{{.*}}],[[REG]]
 ; CHECK-NEXT: mov [[REG:[^,]*]],BYTE PTR [{{.*}}+0x20]
 ; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x20],[[REG]]
 ; CHECK-NOT: mov
 ; ARM32-LABEL: test_memcpy_large_const_len
 ; ARM32: bl {{.*}} memcpy
 
-; TODO(jvoung) -- if we want to be clever, we can do memset without a function
-; call similar to memcpy.
 define void @test_memmove(i32 %iptr_dst, i32 %iptr_src, i32 %len) {
 entry:
   %dst = inttoptr i32 %iptr_dst to i8*
   %src = inttoptr i32 %iptr_src to i8*
   call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
-                                        i32 %len, i32 1, i1 false)
+                                       i32 %len, i32 1, i1 false)
   ret void
 }
 ; CHECK-LABEL: test_memmove
 ; CHECK: call {{.*}} R_{{.*}} memmove
 ; ARM32-LABEL: test_memmove
 ; ARM32: bl {{.*}} memmove
 
-define void @test_memmove_const_len_align(i32 %iptr_dst, i32 %iptr_src) {
+define void @test_memmove_long_const_len(i32 %iptr_dst, i32 %iptr_src) {
 entry:
   %dst = inttoptr i32 %iptr_dst to i8*
   %src = inttoptr i32 %iptr_src to i8*
   call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
-                                        i32 32, i32 1, i1 false)
+                                       i32 4876, i32 1, i1 false)
   ret void
 }
-; CHECK-LABEL: test_memmove_const_len_align
+; CHECK-LABEL: test_memmove_long_const_len
 ; CHECK: call {{.*}} R_{{.*}} memmove
-; ARM32-LABEL: test_memmove_const_len_align
+; ARM32-LABEL: test_memmove_long_const_len
+; ARM32: bl {{.*}} memmove
+
+define void @test_memmove_very_small_const_len(i32 %iptr_dst, i32 %iptr_src) {
+entry:
+  %dst = inttoptr i32 %iptr_dst to i8*
+  %src = inttoptr i32 %iptr_src to i8*
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
+                                       i32 2, i32 1, i1 false)
+  ret void
+}
+; CHECK-LABEL: test_memmove_very_small_const_len
+; CHECK: mov [[REG:[^,]*]],WORD PTR [{{.*}}]
+; CHECK-NEXT: mov WORD PTR [{{.*}}],[[REG]]
+; CHECK-NOT: mov
+; ARM32-LABEL: test_memmove_very_small_const_len
+; ARM32: bl {{.*}} memmove
+
+define void @test_memmove_const_len_3(i32 %iptr_dst, i32 %iptr_src) {
+entry:
+  %dst = inttoptr i32 %iptr_dst to i8*
+  %src = inttoptr i32 %iptr_src to i8*
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
+                                       i32 3, i32 1, i1 false)
+  ret void
+}
+; CHECK-LABEL: test_memmove_const_len_3
+; CHECK: mov [[REG0:[^,]*]],WORD PTR [{{.*}}]
+; CHECK-NEXT: mov [[REG1:[^,]*]],BYTE PTR [{{.*}}+0x2]
+; CHECK-NEXT: mov WORD PTR [{{.*}}],[[REG0]]
+; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x2],[[REG1]]
+; CHECK-NOT: mov
+; ARM32-LABEL: test_memmove_const_len_3
+; ARM32: bl {{.*}} memmove
+
+define void @test_memmove_mid_const_len(i32 %iptr_dst, i32 %iptr_src) {
+entry:
+  %dst = inttoptr i32 %iptr_dst to i8*
+  %src = inttoptr i32 %iptr_src to i8*
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
+                                       i32 9, i32 1, i1 false)
+  ret void
+}
+; CHECK-LABEL: test_memmove_mid_const_len
+; CHECK: movq [[REG0:xmm[0-9]+]],QWORD PTR [{{.*}}]
+; CHECK-NEXT: mov [[REG1:[^,]*]],BYTE PTR [{{.*}}+0x8]
+; CHECK-NEXT: movq QWORD PTR [{{.*}}],[[REG0]]
+; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x8],[[REG1]]
+; CHECK-NOT: mov
+; ARM32-LABEL: test_memmove_mid_const_len
+; ARM32: bl {{.*}} memmove
+
+define void @test_memmove_mid_const_len_overlap(i32 %iptr_dst, i32 %iptr_src) {
+entry:
+  %dst = inttoptr i32 %iptr_dst to i8*
+  %src = inttoptr i32 %iptr_src to i8*
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
+                                       i32 15, i32 1, i1 false)
+  ret void
+}
+; CHECK-LABEL: test_memmove_mid_const_len_overlap
+; CHECK: movq [[REG0:xmm[0-9]+]],QWORD PTR [{{.*}}]
+; CHECK-NEXT: movq [[REG1:xmm[0-9]+]],QWORD PTR [{{.*}}+0x7]
+; CHECK-NEXT: movq QWORD PTR [{{.*}}],[[REG0]]
+; CHECK-NEXT: movq QWORD PTR [{{.*}}+0x7],[[REG1]]
+; CHECK-NOT: mov
+; ARM32-LABEL: test_memmove_mid_const_len_overlap
+; ARM32: bl {{.*}} memmove
+
+define void @test_memmove_large_const_len_overlap(i32 %iptr_dst, i32 %iptr_src) {
+entry:
+  %dst = inttoptr i32 %iptr_dst to i8*
+  %src = inttoptr i32 %iptr_src to i8*
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
+                                       i32 30, i32 1, i1 false)
+  ret void
+}
+; CHECK-LABEL: test_memmove_large_const_len_overlap
+; CHECK: movups [[REG0:xmm[0-9]+]],XMMWORD PTR [{{.*}}]
+; CHECK-NEXT: movups [[REG1:xmm[0-9]+]],XMMWORD PTR [{{.*}}+0xe]
+; CHECK-NEXT: movups XMMWORD PTR [{{.*}}],[[REG0]]
+; CHECK-NEXT: movups XMMWORD PTR [{{.*}}+0xe],[[REG1]]
+; CHECK-NOT: mov
+; ARM32-LABEL: test_memmove_large_const_len_overlap
+; ARM32: bl {{.*}} memmove
+
+define void @test_memmove_large_const_len(i32 %iptr_dst, i32 %iptr_src) {
+entry:
+  %dst = inttoptr i32 %iptr_dst to i8*
+  %src = inttoptr i32 %iptr_src to i8*
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
+                                       i32 33, i32 1, i1 false)
+  ret void
+}
+; CHECK-LABEL: test_memmove_large_const_len
+; CHECK: movups [[REG0:xmm[0-9]+]],XMMWORD PTR [{{.*}}+0x10]
+; CHECK-NEXT: movups [[REG1:xmm[0-9]+]],XMMWORD PTR [{{.*}}]
+; CHECK-NEXT: mov [[REG2:[^,]*]],BYTE PTR [{{.*}}+0x20]
+; CHECK-NEXT: movups XMMWORD PTR [{{.*}}+0x10],[[REG0]]
+; CHECK-NEXT: movups XMMWORD PTR [{{.*}}],[[REG1]]
+; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x20],[[REG2]]
+; CHECK-NOT: mov
+; ARM32-LABEL: test_memmove_large_const_len
 ; ARM32: bl {{.*}} memmove
 
 define void @test_memset(i32 %iptr_dst, i32 %wide_val, i32 %len) {
 entry:
   %val = trunc i32 %wide_val to i8
   %dst = inttoptr i32 %iptr_dst to i8*
   call void @llvm.memset.p0i8.i32(i8* %dst, i8 %val,
                                   i32 %len, i32 1, i1 false)
   ret void
 }
@@ skipping 140 matching lines @@
 }
 ; CHECK-LABEL: test_memset_zero_const_len_large
 ; CHECK: pxor [[ZERO:xmm[0-9]+]],[[ZERO]]
 ; CHECK-NEXT: movups XMMWORD PTR [{{.*}}+0x10],[[ZERO]]
 ; CHECK-NEXT: movups XMMWORD PTR [{{.*}}],[[ZERO]]
 ; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x20],0x0
 ; CHECK-NOT: mov
 ; ARM32-LABEL: test_memset_zero_const_len_large
 ; ARM32: uxtb
 ; ARM32: bl {{.*}} memset