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| 1 //===- subzero/src/IceAssemblerX86BaseImpl.h - base x86 assembler -*- C++ -*-=// | 1 //===- subzero/src/IceAssemblerX86BaseImpl.h - base x86 assembler -*- C++ -*-=// |
| 2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 3 // for details. All rights reserved. Use of this source code is governed by a | 3 // for details. All rights reserved. Use of this source code is governed by a |
| 4 // BSD-style license that can be found in the LICENSE file. | 4 // BSD-style license that can be found in the LICENSE file. |
| 5 // | 5 // |
| 6 // Modified by the Subzero authors. | 6 // Modified by the Subzero authors. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 // | 9 // |
| 10 // The Subzero Code Generator | 10 // The Subzero Code Generator |
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| 3091 emitRex(Ty, addr, reg); | 3091 emitRex(Ty, addr, reg); |
| 3092 emitUint8(0x0F); | 3092 emitUint8(0x0F); |
| 3093 if (isByteSizedArithType(Ty)) | 3093 if (isByteSizedArithType(Ty)) |
| 3094 emitUint8(0xC0); | 3094 emitUint8(0xC0); |
| 3095 else | 3095 else |
| 3096 emitUint8(0xC1); | 3096 emitUint8(0xC1); |
| 3097 emitOperand(gprEncoding(reg), addr); | 3097 emitOperand(gprEncoding(reg), addr); |
| 3098 } | 3098 } |
| 3099 | 3099 |
| 3100 template <class Machine> | 3100 template <class Machine> |
| 3101 void AssemblerX86Base<Machine>::xchg(Type Ty, typename Traits::GPRRegister reg0, |
| 3102 typename Traits::GPRRegister reg1) { |
| 3103 AssemblerBuffer::EnsureCapacity ensured(&Buffer); |
| 3104 if (Ty == IceType_i16) |
| 3105 emitOperandSizeOverride(); |
| 3106 // Use short form if either register is EAX. |
| 3107 if (reg0 == Traits::Encoded_Reg_Accumulator) { |
| 3108 emitRexB(Ty, reg1); |
| 3109 emitUint8(0x90 + gprEncoding(reg1)); |
| 3110 } else if (reg1 == Traits::Encoded_Reg_Accumulator) { |
| 3111 emitRexB(Ty, reg0); |
| 3112 emitUint8(0x90 + gprEncoding(reg0)); |
| 3113 } else { |
| 3114 emitRexRB(Ty, reg0, reg1); |
| 3115 if (isByteSizedArithType(Ty)) |
| 3116 emitUint8(0x86); |
| 3117 else |
| 3118 emitUint8(0x87); |
| 3119 emitRegisterOperand(gprEncoding(reg0), gprEncoding(reg1)); |
| 3120 } |
| 3121 } |
| 3122 |
| 3123 template <class Machine> |
| 3101 void AssemblerX86Base<Machine>::xchg(Type Ty, | 3124 void AssemblerX86Base<Machine>::xchg(Type Ty, |
| 3102 const typename Traits::Address &addr, | 3125 const typename Traits::Address &addr, |
| 3103 typename Traits::GPRRegister reg) { | 3126 typename Traits::GPRRegister reg) { |
| 3104 AssemblerBuffer::EnsureCapacity ensured(&Buffer); | 3127 AssemblerBuffer::EnsureCapacity ensured(&Buffer); |
| 3105 if (Ty == IceType_i16) | 3128 if (Ty == IceType_i16) |
| 3106 emitOperandSizeOverride(); | 3129 emitOperandSizeOverride(); |
| 3107 emitRex(Ty, addr, reg); | 3130 emitRex(Ty, addr, reg); |
| 3108 if (isByteSizedArithType(Ty)) | 3131 if (isByteSizedArithType(Ty)) |
| 3109 emitUint8(0x86); | 3132 emitUint8(0x86); |
| 3110 else | 3133 else |
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| 3319 (void)shifter; | 3342 (void)shifter; |
| 3320 if (Ty == IceType_i16) | 3343 if (Ty == IceType_i16) |
| 3321 emitOperandSizeOverride(); | 3344 emitOperandSizeOverride(); |
| 3322 emitRexB(Ty, operand.rm()); | 3345 emitRexB(Ty, operand.rm()); |
| 3323 emitUint8(isByteSizedArithType(Ty) ? 0xD2 : 0xD3); | 3346 emitUint8(isByteSizedArithType(Ty) ? 0xD2 : 0xD3); |
| 3324 emitOperand(rm, operand); | 3347 emitOperand(rm, operand); |
| 3325 } | 3348 } |
| 3326 | 3349 |
| 3327 } // end of namespace X86Internal | 3350 } // end of namespace X86Internal |
| 3328 } // end of namespace Ice | 3351 } // end of namespace Ice |
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