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Side by Side Diff: src/IceInstX86BaseImpl.h

Issue 1278173009: Inline memove for small constant sizes and refactor memcpy and memset. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 4 months ago
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1 //===- subzero/src/IceInstX86BaseImpl.h - Generic X86 instructions -*- C++ -*=// 1 //===- subzero/src/IceInstX86BaseImpl.h - Generic X86 instructions -*- C++ -*=//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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3195 Str << ", "; 3195 Str << ", ";
3196 this->getSrc(0)->emit(Func); 3196 this->getSrc(0)->emit(Func);
3197 } 3197 }
3198 3198
3199 template <class Machine> 3199 template <class Machine>
3200 void InstX86Xchg<Machine>::emitIAS(const Cfg *Func) const { 3200 void InstX86Xchg<Machine>::emitIAS(const Cfg *Func) const {
3201 assert(this->getSrcSize() == 2); 3201 assert(this->getSrcSize() == 2);
3202 typename InstX86Base<Machine>::Traits::Assembler *Asm = 3202 typename InstX86Base<Machine>::Traits::Assembler *Asm =
3203 Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>(); 3203 Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
3204 Type Ty = this->getSrc(0)->getType(); 3204 Type Ty = this->getSrc(0)->getType();
3205 const auto Mem = 3205 const auto *VarReg1 = llvm::cast<Variable>(this->getSrc(1));
3206 assert(VarReg1->hasReg());
3207 const typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister Reg1 =
3208 InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
3209 VarReg1->getRegNum());
3210
3211 if (const auto *VarReg0 = llvm::dyn_cast<Variable>(this->getSrc(0))) {
3212 assert(VarReg0->hasReg());
3213 const typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister Reg0 =
3214 InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
3215 VarReg0->getRegNum());
3216 Asm->xchg(Ty, Reg0, Reg1);
3217 return;
3218 }
3219
3220 const auto *Mem =
3206 llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>( 3221 llvm::cast<typename InstX86Base<Machine>::Traits::X86OperandMem>(
3207 this->getSrc(0)); 3222 this->getSrc(0));
3208 assert(Mem->getSegmentRegister() == 3223 assert(Mem->getSegmentRegister() ==
3209 InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment); 3224 InstX86Base<Machine>::Traits::X86OperandMem::DefaultSegment);
3210 const typename InstX86Base<Machine>::Traits::Address Addr = 3225 const typename InstX86Base<Machine>::Traits::Address Addr =
3211 Mem->toAsmAddress(Asm); 3226 Mem->toAsmAddress(Asm);
3212 const auto VarReg = llvm::cast<Variable>(this->getSrc(1)); 3227 Asm->xchg(Ty, Addr, Reg1);
3213 assert(VarReg->hasReg());
3214 const typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister Reg =
3215 InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
3216 VarReg->getRegNum());
3217 Asm->xchg(Ty, Addr, Reg);
3218 } 3228 }
3219 3229
3220 template <class Machine> 3230 template <class Machine>
3221 void InstX86Xchg<Machine>::dump(const Cfg *Func) const { 3231 void InstX86Xchg<Machine>::dump(const Cfg *Func) const {
3222 if (!BuildDefs::dump()) 3232 if (!BuildDefs::dump())
3223 return; 3233 return;
3224 Ostream &Str = Func->getContext()->getStrDump(); 3234 Ostream &Str = Func->getContext()->getStrDump();
3225 Type Ty = this->getSrc(0)->getType(); 3235 Type Ty = this->getSrc(0)->getType();
3226 Str << "xchg." << Ty << " "; 3236 Str << "xchg." << Ty << " ";
3227 this->dumpSources(Func); 3237 this->dumpSources(Func);
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3277 return; 3287 return;
3278 Ostream &Str = Func->getContext()->getStrDump(); 3288 Ostream &Str = Func->getContext()->getStrDump();
3279 Str << "IACA_END"; 3289 Str << "IACA_END";
3280 } 3290 }
3281 3291
3282 } // end of namespace X86Internal 3292 } // end of namespace X86Internal
3283 3293
3284 } // end of namespace Ice 3294 } // end of namespace Ice
3285 3295
3286 #endif // SUBZERO_SRC_ICEINSTX86BASEIMPL_H 3296 #endif // SUBZERO_SRC_ICEINSTX86BASEIMPL_H
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