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Side by Side Diff: src/IceAssemblerX86BaseImpl.h

Issue 1278173009: Inline memove for small constant sizes and refactor memcpy and memset. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 4 months ago
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1 //===- subzero/src/IceAssemblerX86BaseImpl.h - base x86 assembler -*- C++ -*-=// 1 //===- subzero/src/IceAssemblerX86BaseImpl.h - base x86 assembler -*- C++ -*-=//
2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
3 // for details. All rights reserved. Use of this source code is governed by a 3 // for details. All rights reserved. Use of this source code is governed by a
4 // BSD-style license that can be found in the LICENSE file. 4 // BSD-style license that can be found in the LICENSE file.
5 // 5 //
6 // Modified by the Subzero authors. 6 // Modified by the Subzero authors.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // The Subzero Code Generator 10 // The Subzero Code Generator
(...skipping 3132 matching lines...) Expand 10 before | Expand all | Expand 10 after
3143 emitRex(Ty, addr, reg); 3143 emitRex(Ty, addr, reg);
3144 emitUint8(0x0F); 3144 emitUint8(0x0F);
3145 if (isByteSizedArithType(Ty)) 3145 if (isByteSizedArithType(Ty))
3146 emitUint8(0xC0); 3146 emitUint8(0xC0);
3147 else 3147 else
3148 emitUint8(0xC1); 3148 emitUint8(0xC1);
3149 emitOperand(gprEncoding(reg), addr); 3149 emitOperand(gprEncoding(reg), addr);
3150 } 3150 }
3151 3151
3152 template <class Machine> 3152 template <class Machine>
3153 void AssemblerX86Base<Machine>::xchg(Type Ty, typename Traits::GPRRegister reg0,
3154 typename Traits::GPRRegister reg1) {
3155 AssemblerBuffer::EnsureCapacity ensured(&Buffer);
3156 if (Ty == IceType_i16)
3157 emitOperandSizeOverride();
3158 // Use short form if either register is EAX.
3159 if (reg0 == Traits::Encoded_Reg_Accumulator) {
3160 emitRexB(Ty, reg1);
3161 emitUint8(0x90 + gprEncoding(reg1));
3162 } else if (reg1 == Traits::Encoded_Reg_Accumulator) {
3163 emitRexB(Ty, reg0);
3164 emitUint8(0x90 + gprEncoding(reg0));
3165 } else {
3166 emitRexRB(Ty, reg0, reg1);
3167 if (isByteSizedArithType(Ty))
3168 emitUint8(0x86);
3169 else
3170 emitUint8(0x87);
3171 emitRegisterOperand(gprEncoding(reg0), gprEncoding(reg1));
3172 }
3173 }
3174
3175 template <class Machine>
3153 void AssemblerX86Base<Machine>::xchg(Type Ty, 3176 void AssemblerX86Base<Machine>::xchg(Type Ty,
3154 const typename Traits::Address &addr, 3177 const typename Traits::Address &addr,
3155 typename Traits::GPRRegister reg) { 3178 typename Traits::GPRRegister reg) {
3156 AssemblerBuffer::EnsureCapacity ensured(&Buffer); 3179 AssemblerBuffer::EnsureCapacity ensured(&Buffer);
3157 if (Ty == IceType_i16) 3180 if (Ty == IceType_i16)
3158 emitOperandSizeOverride(); 3181 emitOperandSizeOverride();
3159 emitRex(Ty, addr, reg); 3182 emitRex(Ty, addr, reg);
3160 if (isByteSizedArithType(Ty)) 3183 if (isByteSizedArithType(Ty))
3161 emitUint8(0x86); 3184 emitUint8(0x86);
3162 else 3185 else
(...skipping 208 matching lines...) Expand 10 before | Expand all | Expand 10 after
3371 (void)shifter; 3394 (void)shifter;
3372 if (Ty == IceType_i16) 3395 if (Ty == IceType_i16)
3373 emitOperandSizeOverride(); 3396 emitOperandSizeOverride();
3374 emitRexB(Ty, operand.rm()); 3397 emitRexB(Ty, operand.rm());
3375 emitUint8(isByteSizedArithType(Ty) ? 0xD2 : 0xD3); 3398 emitUint8(isByteSizedArithType(Ty) ? 0xD2 : 0xD3);
3376 emitOperand(rm, operand); 3399 emitOperand(rm, operand);
3377 } 3400 }
3378 3401
3379 } // end of namespace X86Internal 3402 } // end of namespace X86Internal
3380 } // end of namespace Ice 3403 } // end of namespace Ice
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