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Side by Side Diff: src/IceAssemblerX86Base.h

Issue 1278173009: Inline memove for small constant sizes and refactor memcpy and memset. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 4 months ago
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1 //===- subzero/src/IceAssemblerX86Base.h - base x86 assembler -*- C++ -*---===// 1 //===- subzero/src/IceAssemblerX86Base.h - base x86 assembler -*- C++ -*---===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
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838 void jmp(const ConstantRelocatable *label); // not testable. 838 void jmp(const ConstantRelocatable *label); // not testable.
839 839
840 void mfence(); 840 void mfence();
841 841
842 void lock(); 842 void lock();
843 void cmpxchg(Type Ty, const typename Traits::Address &address, 843 void cmpxchg(Type Ty, const typename Traits::Address &address,
844 typename Traits::GPRRegister reg, bool Locked); 844 typename Traits::GPRRegister reg, bool Locked);
845 void cmpxchg8b(const typename Traits::Address &address, bool Locked); 845 void cmpxchg8b(const typename Traits::Address &address, bool Locked);
846 void xadd(Type Ty, const typename Traits::Address &address, 846 void xadd(Type Ty, const typename Traits::Address &address,
847 typename Traits::GPRRegister reg, bool Locked); 847 typename Traits::GPRRegister reg, bool Locked);
848 void xchg(Type Ty, typename Traits::GPRRegister reg0,
849 typename Traits::GPRRegister reg1);
848 void xchg(Type Ty, const typename Traits::Address &address, 850 void xchg(Type Ty, const typename Traits::Address &address,
849 typename Traits::GPRRegister reg); 851 typename Traits::GPRRegister reg);
850 852
851 /// \name Intel Architecture Code Analyzer markers. 853 /// \name Intel Architecture Code Analyzer markers.
852 /// @{ 854 /// @{
853 void iaca_start(); 855 void iaca_start();
854 void iaca_end(); 856 void iaca_end();
855 /// @} 857 /// @}
856 858
857 void emitSegmentOverride(uint8_t prefix); 859 void emitSegmentOverride(uint8_t prefix);
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1060 emitUint8(0x66); 1062 emitUint8(0x66);
1061 } 1063 }
1062 1064
1063 } // end of namespace X86Internal 1065 } // end of namespace X86Internal
1064 1066
1065 } // end of namespace Ice 1067 } // end of namespace Ice
1066 1068
1067 #include "IceAssemblerX86BaseImpl.h" 1069 #include "IceAssemblerX86BaseImpl.h"
1068 1070
1069 #endif // SUBZERO_SRC_ICEASSEMBLERX86BASE_H 1071 #endif // SUBZERO_SRC_ICEASSEMBLERX86BASE_H
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