Inline memove for small constant sizes and refactor memcpy and memset.

tests_lit/llvm2ice_tests/nacl-mem-intrinsics.ll

 ; This tests the NaCl intrinsics memset, memcpy and memmove.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -sandbox \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -sandbox \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_ARM32 --need=allow_dump \
@@ skipping 127 matching lines @@
 ; CHECK: movups [[REG:xmm[0-9]+]],XMMWORD PTR [{{.*}}+0x10]
 ; CHECK-NEXT: movups XMMWORD PTR [{{.*}}+0x10],[[REG]]
 ; CHECK-NEXT: movups [[REG:xmm[0-9]+]],XMMWORD PTR [{{.*}}]
 ; CHECK-NEXT: movups XMMWORD PTR [{{.*}}],[[REG]]
 ; CHECK-NEXT: mov [[REG:[^,]*]],BYTE PTR [{{.*}}+0x20]
 ; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x20],[[REG]]
 ; CHECK-NOT: mov
 ; ARM32-LABEL: test_memcpy_large_const_len
 ; ARM32: bl {{.*}} memcpy
 
-; TODO(jvoung) -- if we want to be clever, we can do memset without a function
-; call similar to memcpy.
 define void @test_memmove(i32 %iptr_dst, i32 %iptr_src, i32 %len) {
 entry:
   %dst = inttoptr i32 %iptr_dst to i8*
   %src = inttoptr i32 %iptr_src to i8*
   call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
                                         i32 %len, i32 1, i1 false)
   ret void
 }
 ; CHECK-LABEL: test_memmove
 ; CHECK: call {{.*}} R_{{.*}} memmove
 ; ARM32-LABEL: test_memmove
 ; ARM32: bl {{.*}} memmove
 
-define void @test_memmove_const_len_align(i32 %iptr_dst, i32 %iptr_src) {
+define void @test_memmove_long_const_len(i32 %iptr_dst, i32 %iptr_src) {
 entry:
   %dst = inttoptr i32 %iptr_dst to i8*
   %src = inttoptr i32 %iptr_src to i8*
   call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
-                                        i32 32, i32 1, i1 false)
+                                        i32 4876, i32 1, i1 false)
   ret void
 }
-; CHECK-LABEL: test_memmove_const_len_align
+; CHECK-LABEL: test_memmove_long_const_len
 ; CHECK: call {{.*}} R_{{.*}} memmove
-; ARM32-LABEL: test_memmove_const_len_align
+; ARM32-LABEL: test_memmove_long_const_len
+; ARM32: bl {{.*}} memmove
+
+define void @test_memmove_very_small_const_len(i32 %iptr_dst, i32 %iptr_src) {
+entry:
+  %dst = inttoptr i32 %iptr_dst to i8*
+  %src = inttoptr i32 %iptr_src to i8*
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
+                                        i32 2, i32 1, i1 false)
+  ret void
+}
+; CHECK-LABEL: test_memmove_very_small_const_len
+; CHECK: cmp {{.*}},{{.*}}
+; CHECK-NEXT: jb
+; CHECK-NEXT: xchg {{.*}},{{.*}}
+; CHECK-NEXT: mov [[REG:[^,]*]],WORD PTR [{{.*}}]
+; CHECK-NEXT: mov WORD PTR [{{.*}}],[[REG]]
+; CHECK-NOT: mov
+; ARM32-LABEL: test_memmove_very_small_const_len
+; ARM32: bl {{.*}} memmove
+
+define void @test_memmove_const_len_3(i32 %iptr_dst, i32 %iptr_src) {
+entry:
+  %dst = inttoptr i32 %iptr_dst to i8*
+  %src = inttoptr i32 %iptr_src to i8*
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
+                                        i32 3, i32 1, i1 false)
+  ret void
+}
+; CHECK-LABEL: test_memmove_const_len_3
+; CHECK: cmp {{.*}},{{.*}}
+; CHECK-NEXT: jb
+; CHECK-NEXT: xchg {{.*}},{{.*}}
+; CHECK-NEXT: mov [[REG:[^,]*]],WORD PTR [{{.*}}]
+; CHECK-NEXT: mov WORD PTR [{{.*}}],[[REG]]
+; CHECK-NEXT: mov [[REG:[^,]*]],BYTE PTR [{{.*}}+0x2]
+; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x2],[[REG]]
+; CHECK-NOT: mov
+; ARM32-LABEL: test_memmove_const_len_3
+; ARM32: bl {{.*}} memmove
+
+define void @test_memmove_mid_const_len(i32 %iptr_dst, i32 %iptr_src) {
+entry:
+  %dst = inttoptr i32 %iptr_dst to i8*
+  %src = inttoptr i32 %iptr_src to i8*
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
+                                        i32 9, i32 1, i1 false)
+  ret void
+}
+; CHECK-LABEL: test_memmove_mid_const_len
+; CHECK: cmp {{.*}},{{.*}}
+; CHECK-NEXT: jb
+; CHECK-NEXT: xchg {{.*}},{{.*}}
+; CHECK-NEXT: movq [[REG:xmm[0-9]+]],QWORD PTR [{{.*}}]
+; CHECK-NEXT: movq QWORD PTR [{{.*}}],[[REG]]
+; CHECK-NEXT: mov [[REG:[^,]*]],BYTE PTR [{{.*}}+0x8]
+; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x8],[[REG]]
+; CHECK-NOT: mov
+; ARM32-LABEL: test_memmove_mid_const_len
+; ARM32: bl {{.*}} memmove
+
+define void @test_memmove_mid_const_len_no_overlap(i32 %iptr_dst, i32 %iptr_src) {
+entry:
+  %dst = inttoptr i32 %iptr_dst to i8*
+  %src = inttoptr i32 %iptr_src to i8*
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
+                                        i32 15, i32 1, i1 false)
+  ret void
+}
+; CHECK-LABEL: test_memmove_mid_const_len_no_overlap
+; CHECK: cmp {{.*}},{{.*}}
+; CHECK-NEXT: jb
+; CHECK-NEXT: xchg {{.*}},{{.*}}
+; CHECK-NEXT: movq [[REG:xmm[0-9]+]],QWORD PTR [{{.*}}]
+; CHECK-NEXT: movq QWORD PTR [{{.*}}],[[REG]]
+; CHECK-NEXT: mov [[REG:[^,]*]],DWORD PTR [{{.*}}+0x8]
+; CHECK-NEXT: mov DWORD PTR [{{.*}}+0x8],[[REG]]
+; CHECK-NEXT: mov [[REG:[^,]*]],WORD PTR [{{.*}}+0xc]
+; CHECK: mov WORD PTR [{{.*}}+0xc],[[REG]]

[Jim Stichnoth, 2015/08/12 13:41:47]

Is this a CHECK instead of CHECK-NEXT because sandboxing?  If so, add a comment.

Also, to maximize the chances of the lowering sequence fitting into a bundle,
put a bogus call before the memmove call, so that the memmove lowering sequence
is forced to start at a new bundle boundary.  (But note that adding a call may
make register allocation harder/worse.)

It's unlikely that future changes separate from memmove lowering would increase
the code size, but if they accidentally do and that causes memmove spillover
into a new bundle, then I guess these tests would be a canary for that.

[ascull, 2015/08/17 22:18:53]

With the new (and correct) implementation on memmove this test is not longer of
interest so has been removed. I'll keep this trick in mind for use in future
though.

+; CHECK-NEXT: mov [[REG:[^,]*]],BYTE PTR [{{.*}}+0xe]
+; CHECK-NEXT: mov BYTE PTR [{{.*}}+0xe],[[REG]]
+; CHECK-NOT: mov
+; ARM32-LABEL: test_memmove_mid_const_len_no_overlap
+; ARM32: bl {{.*}} memmove
+
+define void @test_memmove_big_const_len_no_overlap(i32 %iptr_dst, i32 %iptr_src) {
+entry:
+  %dst = inttoptr i32 %iptr_dst to i8*
+  %src = inttoptr i32 %iptr_src to i8*
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
+                                        i32 30, i32 1, i1 false)
+  ret void
+}
+; CHECK-LABEL: test_memmove_big_const_len_no_overlap
+; CHECK: cmp {{.*}},{{.*}}
+; CHECK-NEXT: jb
+; CHECK-NEXT: xchg {{.*}},{{.*}}
+; CHECK-NEXT: movups [[REG:xmm[0-9]+]],XMMWORD PTR [{{.*}}]
+; CHECK-NEXT: movups XMMWORD PTR [{{.*}}],[[REG]]
+; CHECK-NEXT: movq [[REG:xmm[0-9]+]],QWORD PTR [{{.*}}+0x10]
+; CHECK-NEXT: movq QWORD PTR [{{.*}}+0x10],[[REG]]
+; CHECK-NEXT: mov [[REG:[^,]*]],DWORD PTR [{{.*}}+0x18]
+; CHECK-NEXT: mov DWORD PTR [{{.*}}+0x18],[[REG]]
+; CHECK-NEXT: mov [[REG:[^,]*]],WORD PTR [{{.*}}+0x1c]
+; CHECK-NEXT: mov WORD PTR [{{.*}}+0x1c],[[REG]]
+; CHECK-NOT: mov
+; ARM32-LABEL: test_memmove_big_const_len_no_overlap
+; ARM32: bl {{.*}} memmove
+
+define void @test_memmove_large_const_len(i32 %iptr_dst, i32 %iptr_src) {
+entry:
+  %dst = inttoptr i32 %iptr_dst to i8*
+  %src = inttoptr i32 %iptr_src to i8*
+  call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
+                                        i32 33, i32 1, i1 false)
+  ret void
+}
+; CHECK-LABEL: test_memmove_large_const_len
+; CHECK: cmp {{.*}},{{.*}}
+; CHECK-NEXT: jb
+; CHECK-NEXT: xchg {{.*}},{{.*}}
+; CHECK-NEXT: movups [[REG:xmm[0-9]+]],XMMWORD PTR [{{.*}}]
+; CHECK-NEXT: movups XMMWORD PTR [{{.*}}],[[REG]]
+; CHECK-NEXT: movups [[REG:xmm[0-9]+]],XMMWORD PTR [{{.*}}+0x10]
+; CHECK-NEXT: movups XMMWORD PTR [{{.*}}+0x10],[[REG]]
+; CHECK-NEXT: mov [[REG:[^,]*]],BYTE PTR [{{.*}}+0x20]
+; CHECK: mov BYTE PTR [{{.*}}+0x20],[[REG]]
+; CHECK-NOT: mov
+; ARM32-LABEL: test_memmove_large_const_len
 ; ARM32: bl {{.*}} memmove
 
 define void @test_memset(i32 %iptr_dst, i32 %wide_val, i32 %len) {
 entry:
   %val = trunc i32 %wide_val to i8
   %dst = inttoptr i32 %iptr_dst to i8*
   call void @llvm.memset.p0i8.i32(i8* %dst, i8 %val,
                                   i32 %len, i32 1, i1 false)
   ret void
 }
@@ skipping 140 matching lines @@
 }
 ; CHECK-LABEL: test_memset_zero_const_len_large
 ; CHECK: pxor [[ZERO:xmm[0-9]+]],[[ZERO]]
 ; CHECK-NEXT: movups XMMWORD PTR [{{.*}}+0x10],[[ZERO]]
 ; CHECK-NEXT: movups XMMWORD PTR [{{.*}}],[[ZERO]]
 ; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x20],0x0
 ; CHECK-NOT: mov
 ; ARM32-LABEL: test_memset_zero_const_len_large
 ; ARM32: uxtb
 ; ARM32: bl {{.*}} memset