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1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_ARM64_MACRO_ASSEMBLER_ARM64_INL_H_ | 5 #ifndef V8_ARM64_MACRO_ASSEMBLER_ARM64_INL_H_ |
6 #define V8_ARM64_MACRO_ASSEMBLER_ARM64_INL_H_ | 6 #define V8_ARM64_MACRO_ASSEMBLER_ARM64_INL_H_ |
7 | 7 |
8 #include <ctype.h> | 8 #include <ctype.h> |
9 | 9 |
10 #include "src/globals.h" | 10 #include "src/globals.h" |
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862 hlt(code); | 862 hlt(code); |
863 } | 863 } |
864 | 864 |
865 | 865 |
866 void MacroAssembler::Isb() { | 866 void MacroAssembler::Isb() { |
867 DCHECK(allow_macro_instructions_); | 867 DCHECK(allow_macro_instructions_); |
868 isb(); | 868 isb(); |
869 } | 869 } |
870 | 870 |
871 | 871 |
872 void MacroAssembler::Ldnp(const CPURegister& rt, | |
873 const CPURegister& rt2, | |
874 const MemOperand& src) { | |
875 DCHECK(allow_macro_instructions_); | |
876 DCHECK(!AreAliased(rt, rt2)); | |
877 ldnp(rt, rt2, src); | |
878 } | |
879 | |
880 | |
881 void MacroAssembler::Ldr(const CPURegister& rt, const Immediate& imm) { | 872 void MacroAssembler::Ldr(const CPURegister& rt, const Immediate& imm) { |
882 DCHECK(allow_macro_instructions_); | 873 DCHECK(allow_macro_instructions_); |
883 ldr(rt, imm); | 874 ldr(rt, imm); |
884 } | 875 } |
885 | 876 |
886 | 877 |
887 void MacroAssembler::Ldr(const CPURegister& rt, double imm) { | 878 void MacroAssembler::Ldr(const CPURegister& rt, double imm) { |
888 DCHECK(allow_macro_instructions_); | 879 DCHECK(allow_macro_instructions_); |
889 DCHECK(rt.Is64Bits()); | 880 DCHECK(rt.Is64Bits()); |
890 ldr(rt, Immediate(double_to_rawbits(imm))); | 881 ldr(rt, Immediate(double_to_rawbits(imm))); |
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1127 | 1118 |
1128 | 1119 |
1129 void MacroAssembler::Umull(const Register& rd, const Register& rn, | 1120 void MacroAssembler::Umull(const Register& rd, const Register& rn, |
1130 const Register& rm) { | 1121 const Register& rm) { |
1131 DCHECK(allow_macro_instructions_); | 1122 DCHECK(allow_macro_instructions_); |
1132 DCHECK(!rd.IsZero()); | 1123 DCHECK(!rd.IsZero()); |
1133 umaddl(rd, rn, rm, xzr); | 1124 umaddl(rd, rn, rm, xzr); |
1134 } | 1125 } |
1135 | 1126 |
1136 | 1127 |
1137 void MacroAssembler::Stnp(const CPURegister& rt, | |
1138 const CPURegister& rt2, | |
1139 const MemOperand& dst) { | |
1140 DCHECK(allow_macro_instructions_); | |
1141 stnp(rt, rt2, dst); | |
1142 } | |
1143 | |
1144 | |
1145 void MacroAssembler::Sxtb(const Register& rd, const Register& rn) { | 1128 void MacroAssembler::Sxtb(const Register& rd, const Register& rn) { |
1146 DCHECK(allow_macro_instructions_); | 1129 DCHECK(allow_macro_instructions_); |
1147 DCHECK(!rd.IsZero()); | 1130 DCHECK(!rd.IsZero()); |
1148 sxtb(rd, rn); | 1131 sxtb(rd, rn); |
1149 } | 1132 } |
1150 | 1133 |
1151 | 1134 |
1152 void MacroAssembler::Sxth(const Register& rd, const Register& rn) { | 1135 void MacroAssembler::Sxth(const Register& rd, const Register& rn) { |
1153 DCHECK(allow_macro_instructions_); | 1136 DCHECK(allow_macro_instructions_); |
1154 DCHECK(!rd.IsZero()); | 1137 DCHECK(!rd.IsZero()); |
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1696 // characters are reserved for controlling features of the instrumentation. | 1679 // characters are reserved for controlling features of the instrumentation. |
1697 DCHECK(isprint(marker_name[0]) && isprint(marker_name[1])); | 1680 DCHECK(isprint(marker_name[0]) && isprint(marker_name[1])); |
1698 | 1681 |
1699 InstructionAccurateScope scope(this, 1); | 1682 InstructionAccurateScope scope(this, 1); |
1700 movn(xzr, (marker_name[1] << 8) | marker_name[0]); | 1683 movn(xzr, (marker_name[1] << 8) | marker_name[0]); |
1701 } | 1684 } |
1702 | 1685 |
1703 } } // namespace v8::internal | 1686 } } // namespace v8::internal |
1704 | 1687 |
1705 #endif // V8_ARM64_MACRO_ASSEMBLER_ARM64_INL_H_ | 1688 #endif // V8_ARM64_MACRO_ASSEMBLER_ARM64_INL_H_ |
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