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| 1 //===- ARMMCNaClExpander.cpp ------------------------------------*- C++ -*-===// | 1 //===- ARMMCNaClExpander.cpp ------------------------------------*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The LLVM Compiler Infrastructure | 3 // The LLVM Compiler Infrastructure |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 // | 9 // |
| 10 // This file implements the ARMMCNaClExpander class, the ARM specific | 10 // This file implements the ARMMCNaClExpander class, the ARM specific |
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| 21 #include "llvm/MC/MCNaClExpander.h" | 21 #include "llvm/MC/MCNaClExpander.h" |
| 22 #include "llvm/MC/MCObjectFileInfo.h" | 22 #include "llvm/MC/MCObjectFileInfo.h" |
| 23 #include "llvm/MC/MCRegisterInfo.h" | 23 #include "llvm/MC/MCRegisterInfo.h" |
| 24 #include "llvm/MC/MCStreamer.h" | 24 #include "llvm/MC/MCStreamer.h" |
| 25 | 25 |
| 26 using namespace llvm; | 26 using namespace llvm; |
| 27 | 27 |
| 28 const unsigned kBranchTargetMask = 0xC000000F; | 28 const unsigned kBranchTargetMask = 0xC000000F; |
| 29 const unsigned kSandboxMask = 0xC0000000; | 29 const unsigned kSandboxMask = 0xC0000000; |
| 30 | 30 |
| 31 bool ARM::ARMMCNaClExpander::isValidScratchRegister(unsigned Reg) const { |
| 32 // TODO(dschuff): Also check the regster class. |
| 33 return Reg != ARM::PC && Reg != ARM::SP; |
| 34 } |
| 35 |
| 31 static void emitBicMask(unsigned Mask, unsigned Reg, ARMCC::CondCodes Pred, | 36 static void emitBicMask(unsigned Mask, unsigned Reg, ARMCC::CondCodes Pred, |
| 32 unsigned PredReg, MCStreamer &Out, | 37 unsigned PredReg, MCStreamer &Out, |
| 33 const MCSubtargetInfo &STI) { | 38 const MCSubtargetInfo &STI) { |
| 34 MCInst Bic; | 39 MCInst Bic; |
| 35 const int32_t EncodedMask = ARM_AM::getSOImmVal(Mask); | 40 const int32_t EncodedMask = ARM_AM::getSOImmVal(Mask); |
| 36 Bic.setOpcode(ARM::BICri); | 41 Bic.setOpcode(ARM::BICri); |
| 37 Bic.addOperand(MCOperand::CreateReg(Reg)); | 42 Bic.addOperand(MCOperand::CreateReg(Reg)); |
| 38 Bic.addOperand(MCOperand::CreateReg(Reg)); | 43 Bic.addOperand(MCOperand::CreateReg(Reg)); |
| 39 Bic.addOperand(MCOperand::CreateImm(EncodedMask)); | 44 Bic.addOperand(MCOperand::CreateImm(EncodedMask)); |
| 40 Bic.addOperand(MCOperand::CreateImm(Pred)); | 45 Bic.addOperand(MCOperand::CreateImm(Pred)); |
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| 195 const MCSubtargetInfo &STI) { | 200 const MCSubtargetInfo &STI) { |
| 196 if (Guard) | 201 if (Guard) |
| 197 return false; | 202 return false; |
| 198 Guard = true; | 203 Guard = true; |
| 199 | 204 |
| 200 doExpandInst(Inst, Out, STI); | 205 doExpandInst(Inst, Out, STI); |
| 201 | 206 |
| 202 Guard = false; | 207 Guard = false; |
| 203 return true; | 208 return true; |
| 204 } | 209 } |
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