Auto-sandboxing: Switch to automatic scratch register invalidation

lib/Target/X86/MCTargetDesc/X86MCNaClExpander.cpp

 //===- X86MCNaClExpander.cpp ------------------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the X86MCNaClExpander class, the X86 specific
@@ skipping 21 matching lines @@
 unsigned getReg64(unsigned Reg);
 
 static unsigned demoteOpcode(unsigned Reg);
 
 static bool isAbsoluteReg(unsigned Reg) {
   Reg = getReg64(Reg); // Normalize to 64 bits
   return (Reg == X86::R15 || Reg == X86::RSP || Reg == X86::RBP ||
           Reg == X86::RIP);
 }
 
+bool X86::X86MCNaClExpander::isValidScratchRegister(unsigned Reg) const {
+  // TODO(dschuff): Check the register class.
+  if (isAbsoluteReg(Reg))
+    return false;
+  return true;
+}
+
+
 static void PushReturnAddress(const llvm::MCSubtargetInfo &STI,
                               MCContext &Context, MCStreamer &Out,
                               MCSymbol *RetTarget) {
   const MCExpr *RetTargetExpr = MCSymbolRefExpr::Create(RetTarget, Context);
   if (Context.getObjectFileInfo()->getRelocM() == Reloc::PIC_) {
     // Calculate return_addr
     // The return address should not be calculated into R11 because if the push
     // instruction ends up at the start of a bundle, an attacker could arrange
     // an indirect jump to it, which would push the full jump target
     // (which itself was calculated into r11) onto the stack.
@@ skipping 506 matching lines @@
                                              const MCSubtargetInfo &STI,
                                              bool EmitPrefixes) {
   if (EmitPrefixes) {
     for (const MCInst &Prefix : Prefixes)
       Out.EmitInstruction(Prefix, STI);
     Prefixes.clear();
   }
   Out.EmitInstruction(Inst, STI);
 }
 
+
 void X86::X86MCNaClExpander::doExpandInst(const MCInst &Inst, MCStreamer &Out,
                                           const MCSubtargetInfo &STI,
                                           bool EmitPrefixes) {
 
+
   // Explicitly IGNORE all pseudo instructions, these will be handled in the
   // older customExpandInst code
   switch (Inst.getOpcode()) {
   case X86::CALLpcrel32:
   case X86::CALL64pcrel32:
   case X86::NACL_CALL64d:
   case X86::NACL_CALL32r:
   case X86::NACL_CALL64r:
   case X86::NACL_JMP32r:
   case X86::NACL_JMP64r:
@@ skipping 46 matching lines @@
   }
 }
 
 bool X86::X86MCNaClExpander::expandInst(const MCInst &Inst, MCStreamer &Out,
                                         const MCSubtargetInfo &STI) {
   if (Guard)
     return false;
   Guard = true;
 
   doExpandInst(Inst, Out, STI, true);
+  invalidateScratchRegs(Inst);
 
   Guard = false;
   return true;
 }
 
 static unsigned demoteOpcode(unsigned Opcode) {
   switch (Opcode) {
   case X86::ADC64rr:
     return X86::ADC32rr;
   case X86::ADC64ri8:
@@ skipping 531 matching lines @@
   case X86::XOR64ri8:
     return X86::XOR32ri8;
   case X86::XOR64ri32:
     return X86::XOR32ri;
   case X86::XOR64rm:
     return X86::XOR32rm;
   default:
     return Opcode;
   }
 }