Auto-sandboxing: Switch to automatic scratch register invalidation

lib/Target/ARM/MCTargetDesc/ARMMCNaClExpander.cpp

 //===- ARMMCNaClExpander.cpp ------------------------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the ARMMCNaClExpander class, the ARM specific
@@ skipping 10 matching lines @@
 #include "llvm/MC/MCNaClExpander.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 
 using namespace llvm;
 
 const unsigned kBranchTargetMask = 0xC000000F;
 const unsigned kAlwaysPredicate = 14;
 
+bool ARM::ARMMCNaClExpander::isValidScratchRegister(unsigned Reg) const {
+  return true;
+}
+

[dominickd, 2015/08/06 17:45:20]

Shouldn't PC or SP return false?

[Derek Schuff, 2015/08/06 20:46:01]

Yes. I had a // TODO(dschuff): implement
there because I didn't have any tests and I started this before you had any
actual ARM logic checked in. I'll go ahead and put that in now though.

 static void emitBicMask(unsigned Mask, unsigned Reg, int64_t Pred,
                         MCStreamer &Out, const MCSubtargetInfo &STI) {
   MCInst Bic;
   const int32_t EncodedMask = ARM_AM::getSOImmVal(Mask);
   Bic.setOpcode(ARM::BICri);
   Bic.addOperand(MCOperand::CreateReg(Reg));
   Bic.addOperand(MCOperand::CreateReg(Reg));
   Bic.addOperand(MCOperand::CreateImm(EncodedMask));
   Bic.addOperand(MCOperand::CreateImm(Pred));
   Bic.addOperand(MCOperand::CreateReg(ARM::CPSR));
@@ skipping 84 matching lines @@
                                         const MCSubtargetInfo &STI) {
   if (Guard)
     return false;
   Guard = true;
 
   doExpandInst(Inst, Out, STI);
 
   Guard = false;
   return true;
 }