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Side by Side Diff: unittest/AssemblerX8664/XmmArith.cpp

Issue 1273153002: Subzero. Native 64-bit int arithmetic on x86-64. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fixes tests & make format Created 5 years, 4 months ago
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1 //===- subzero/unittest/AssemblerX8664/XmmArith.cpp -----------------------===// 1 //===- subzero/unittest/AssemblerX8664/XmmArith.cpp -----------------------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 #include "AssemblerX8664/TestUtil.h" 9 #include "AssemblerX8664/TestUtil.h"
10 10
(...skipping 1086 matching lines...) Expand 10 before | Expand all | Expand 10 after
1097 \ 1097 \
1098 AssembledTest test = assemble(); \ 1098 AssembledTest test = assemble(); \
1099 test.setDqwordTo(T0, Inst##Size##DstValue); \ 1099 test.setDqwordTo(T0, Inst##Size##DstValue); \
1100 test.setDqwordTo(T1, Inst##Size##SrcValue); \ 1100 test.setDqwordTo(T1, Inst##Size##SrcValue); \
1101 test.run(); \ 1101 test.run(); \
1102 \ 1102 \
1103 ASSERT_EQ(Inst##Size##Expected, test.Dst<Dqword>()) << TestString; \ 1103 ASSERT_EQ(Inst##Size##Expected, test.Dst<Dqword>()) << TestString; \
1104 reset(); \ 1104 reset(); \
1105 } while (0) 1105 } while (0)
1106 1106
1107 #define TestImplSXmmReg(Dst, GPR, Inst, Size) \ 1107 #define TestImplSXmmReg(Dst, GPR, Inst, Size, IntType) \
1108 do { \ 1108 do { \
1109 static constexpr char TestString[] = \ 1109 static constexpr char TestString[] = \
1110 "(" #Dst ", " #GPR ", cvt" #Inst ", f" #Size ")"; \ 1110 "(" #Dst ", " #GPR ", cvt" #Inst ", " #IntType ", f" #Size ")"; \
1111 const uint32_t T0 = allocateDqword(); \ 1111 const uint32_t T0 = allocateDqword(); \
1112 \ 1112 \
1113 __ movups(Encoded_Xmm_##Dst(), dwordAddress(T0)); \ 1113 __ movups(Encoded_Xmm_##Dst(), dwordAddress(T0)); \
1114 __ mov(IceType_i32, Encoded_GPR_##GPR(), Immediate(Inst##Size##SrcValue)); \ 1114 __ mov(IceType_i32, Encoded_GPR_##GPR(), Immediate(Inst##Size##SrcValue)); \
1115 __ cvt##Inst(IceType_f##Size, Encoded_Xmm_##Dst(), Encoded_GPR_##GPR()); \ 1115 __ cvt##Inst(IceType_f##Size, Encoded_Xmm_##Dst(), IntType, \
1116 Encoded_GPR_##GPR()); \
1116 \ 1117 \
1117 AssembledTest test = assemble(); \ 1118 AssembledTest test = assemble(); \
1118 test.setDqwordTo(T0, Inst##Size##DstValue); \ 1119 test.setDqwordTo(T0, Inst##Size##DstValue); \
1119 test.run(); \ 1120 test.run(); \
1120 \ 1121 \
1121 ASSERT_EQ(Inst##Size##Expected, test.Dst<Dqword>()) << TestString; \ 1122 ASSERT_EQ(Inst##Size##Expected, test.Dst<Dqword>()) << TestString; \
1122 reset(); \ 1123 reset(); \
1123 } while (0) 1124 } while (0)
1124 1125
1125 #define TestImplSRegXmm(GPR, Src, Inst, Size) \ 1126 #define TestImplSRegXmm(GPR, Src, Inst, IntSize, Size) \
1126 do { \ 1127 do { \
1127 static constexpr char TestString[] = \ 1128 static constexpr char TestString[] = \
1128 "(" #GPR ", " #Src ", cvt" #Inst ", f" #Size ")"; \ 1129 "(" #GPR ", " #Src ", cvt" #Inst ", " #IntSize ", f" #Size ")"; \
1129 const uint32_t T0 = allocateDqword(); \ 1130 const uint32_t T0 = allocateDqword(); \
1130 \ 1131 \
1131 __ mov(IceType_i32, Encoded_GPR_##GPR(), Immediate(Inst##Size##DstValue)); \ 1132 __ mov(IceType_i32, Encoded_GPR_##GPR(), Immediate(Inst##Size##DstValue)); \
1132 __ movups(Encoded_Xmm_##Src(), dwordAddress(T0)); \ 1133 __ movups(Encoded_Xmm_##Src(), dwordAddress(T0)); \
1133 __ cvt##Inst(IceType_f##Size, Encoded_GPR_##GPR(), Encoded_Xmm_##Src()); \ 1134 __ cvt##Inst(IceType_i##IntSize, Encoded_GPR_##GPR(), IceType_f##Size, \
1135 Encoded_Xmm_##Src()); \
1134 \ 1136 \
1135 AssembledTest test = assemble(); \ 1137 AssembledTest test = assemble(); \
1136 test.setDqwordTo(T0, Inst##Size##SrcValue); \ 1138 test.setDqwordTo(T0, Inst##Size##SrcValue); \
1137 test.run(); \ 1139 test.run(); \
1138 \ 1140 \
1139 ASSERT_EQ(static_cast<uint32_t>(Inst##Size##Expected), test.GPR()) \ 1141 ASSERT_EQ(static_cast<uint##IntSize##_t>(Inst##Size##Expected), \
1142 test.GPR()) \
1140 << TestString; \ 1143 << TestString; \
1141 reset(); \ 1144 reset(); \
1142 } while (0) 1145 } while (0)
1143 1146
1144 #define TestImplPXmmAddr(Dst, Inst, Size) \ 1147 #define TestImplPXmmAddr(Dst, Inst, Size) \
1145 do { \ 1148 do { \
1146 static constexpr char TestString[] = \ 1149 static constexpr char TestString[] = \
1147 "(" #Dst ", Addr, cvt" #Inst ", f" #Size ")"; \ 1150 "(" #Dst ", Addr, cvt" #Inst ", f" #Size ")"; \
1148 const uint32_t T0 = allocateDqword(); \ 1151 const uint32_t T0 = allocateDqword(); \
1149 const uint32_t T1 = allocateDqword(); \ 1152 const uint32_t T1 = allocateDqword(); \
1150 \ 1153 \
1151 __ movups(Encoded_Xmm_##Dst(), dwordAddress(T0)); \ 1154 __ movups(Encoded_Xmm_##Dst(), dwordAddress(T0)); \
1152 __ cvt##Inst(IceType_f##Size, Encoded_Xmm_##Dst(), dwordAddress(T1)); \ 1155 __ cvt##Inst(IceType_f##Size, Encoded_Xmm_##Dst(), dwordAddress(T1)); \
1153 \ 1156 \
1154 AssembledTest test = assemble(); \ 1157 AssembledTest test = assemble(); \
1155 test.setDqwordTo(T0, Inst##Size##DstValue); \ 1158 test.setDqwordTo(T0, Inst##Size##DstValue); \
1156 test.setDqwordTo(T1, Inst##Size##SrcValue); \ 1159 test.setDqwordTo(T1, Inst##Size##SrcValue); \
1157 test.run(); \ 1160 test.run(); \
1158 \ 1161 \
1159 ASSERT_EQ(Inst##Size##Expected, test.Dst<Dqword>()) << TestString; \ 1162 ASSERT_EQ(Inst##Size##Expected, test.Dst<Dqword>()) << TestString; \
1160 reset(); \ 1163 reset(); \
1161 } while (0) 1164 } while (0)
1162 1165
1163 #define TestImplSXmmAddr(Dst, Inst, Size) \ 1166 #define TestImplSXmmAddr(Dst, Inst, Size, IntType) \
1164 do { \ 1167 do { \
1165 static constexpr char TestString[] = \ 1168 static constexpr char TestString[] = \
1166 "(" #Dst ", Addr, cvt" #Inst ", f" #Size ")"; \ 1169 "(" #Dst ", Addr, cvt" #Inst ", f" #Size ", " #IntType ")"; \
1167 const uint32_t T0 = allocateDqword(); \ 1170 const uint32_t T0 = allocateDqword(); \
1168 const uint32_t T1 = allocateDword(); \ 1171 const uint32_t T1 = allocateDword(); \
1169 \ 1172 \
1170 __ movups(Encoded_Xmm_##Dst(), dwordAddress(T0)); \ 1173 __ movups(Encoded_Xmm_##Dst(), dwordAddress(T0)); \
1171 __ cvt##Inst(IceType_f##Size, Encoded_Xmm_##Dst(), dwordAddress(T1)); \ 1174 __ cvt##Inst(IceType_f##Size, Encoded_Xmm_##Dst(), IntType, \
1175 dwordAddress(T1)); \
1172 \ 1176 \
1173 AssembledTest test = assemble(); \ 1177 AssembledTest test = assemble(); \
1174 test.setDqwordTo(T0, Inst##Size##DstValue); \ 1178 test.setDqwordTo(T0, Inst##Size##DstValue); \
1175 test.setDwordTo(T1, Inst##Size##SrcValue); \ 1179 test.setDwordTo(T1, Inst##Size##SrcValue); \
1176 test.run(); \ 1180 test.run(); \
1177 \ 1181 \
1178 ASSERT_EQ(Inst##Size##Expected, test.Dst<Dqword>()) << TestString; \ 1182 ASSERT_EQ(Inst##Size##Expected, test.Dst<Dqword>()) << TestString; \
1179 reset(); \ 1183 reset(); \
1180 } while (0) 1184 } while (0)
1181 1185
1182 #define TestImplSRegAddr(GPR, Inst, Size) \ 1186 #define TestImplSRegAddr(GPR, Inst, IntSize, Size) \
1183 do { \ 1187 do { \
1184 static constexpr char TestString[] = \ 1188 static constexpr char TestString[] = \
1185 "(" #GPR ", Addr, cvt" #Inst ", f" #Size ")"; \ 1189 "(" #GPR ", Addr, cvt" #Inst ", f" #Size ", " #IntSize ")"; \
1186 const uint32_t T0 = allocateDqword(); \ 1190 const uint32_t T0 = allocateDqword(); \
1187 \ 1191 \
1188 __ mov(IceType_i32, Encoded_GPR_##GPR(), Immediate(Inst##Size##DstValue)); \ 1192 __ mov(IceType_i32, Encoded_GPR_##GPR(), Immediate(Inst##Size##DstValue)); \
1189 __ cvt##Inst(IceType_f##Size, Encoded_GPR_##GPR(), dwordAddress(T0)); \ 1193 __ cvt##Inst(IceType_i##IntSize, Encoded_GPR_##GPR(), IceType_f##Size, \
1194 dwordAddress(T0)); \
1190 \ 1195 \
1191 AssembledTest test = assemble(); \ 1196 AssembledTest test = assemble(); \
1192 test.setDqwordTo(T0, Inst##Size##SrcValue); \ 1197 test.setDqwordTo(T0, Inst##Size##SrcValue); \
1193 test.run(); \ 1198 test.run(); \
1194 \ 1199 \
1195 ASSERT_EQ(static_cast<uint32_t>(Inst##Size##Expected), test.GPR()) \ 1200 ASSERT_EQ(static_cast<uint##IntSize##_t>(Inst##Size##Expected), \
1201 test.GPR()) \
1196 << TestString; \ 1202 << TestString; \
1197 reset(); \ 1203 reset(); \
1198 } while (0) 1204 } while (0)
1199 1205
1200 #define TestImplSize(Dst, Src, GPR, Size) \ 1206 #define TestImplSize(Dst, Src, GPR, Size) \
1201 do { \ 1207 do { \
1202 TestImplPXmmXmm(Dst, Src, dq2ps, Size); \ 1208 TestImplPXmmXmm(Dst, Src, dq2ps, Size); \
1203 TestImplPXmmAddr(Src, dq2ps, Size); \ 1209 TestImplPXmmAddr(Src, dq2ps, Size); \
1204 TestImplPXmmXmm(Dst, Src, tps2dq, Size); \ 1210 TestImplPXmmXmm(Dst, Src, tps2dq, Size); \
1205 TestImplPXmmAddr(Src, tps2dq, Size); \ 1211 TestImplPXmmAddr(Src, tps2dq, Size); \
1206 TestImplSXmmReg(Dst, GPR, si2ss, Size); \ 1212 TestImplSXmmReg(Dst, GPR, si2ss, Size, IceType_i32); \
1207 TestImplSXmmAddr(Dst, si2ss, Size); \ 1213 TestImplSXmmReg(Dst, GPR, si2ss, Size, IceType_i64); \
1208 TestImplSRegXmm(GPR, Src, tss2si, Size); \ 1214 TestImplSXmmAddr(Dst, si2ss, Size, IceType_i32); \
1209 TestImplSRegAddr(GPR, tss2si, Size); \ 1215 TestImplSXmmAddr(Dst, si2ss, Size, IceType_i64); \
1216 TestImplSRegXmm(GPR, Src, tss2si, 32, Size); \
1217 TestImplSRegXmm(GPR, Src, tss2si, 64, Size); \
1218 TestImplSRegAddr(GPR, tss2si, 32, Size); \
1219 TestImplSRegAddr(GPR, tss2si, 64, Size); \
1210 TestImplPXmmXmm(Dst, Src, float2float, Size); \ 1220 TestImplPXmmXmm(Dst, Src, float2float, Size); \
1211 TestImplPXmmAddr(Src, float2float, Size); \ 1221 TestImplPXmmAddr(Src, float2float, Size); \
1212 } while (0) 1222 } while (0)
1213 1223
1214 #define TestImpl(Dst, Src, GPR) \ 1224 #define TestImpl(Dst, Src, GPR) \
1215 do { \ 1225 do { \
1216 TestImplSize(Dst, Src, GPR, 32); \ 1226 TestImplSize(Dst, Src, GPR, 32); \
1217 TestImplSize(Dst, Src, GPR, 64); \ 1227 TestImplSize(Dst, Src, GPR, 64); \
1218 } while (0) 1228 } while (0)
1219 1229
(...skipping 685 matching lines...) Expand 10 before | Expand all | Expand 10 after
1905 TestImpl(xmm14, r1, 101); 1915 TestImpl(xmm14, r1, 101);
1906 TestImpl(xmm15, r2, 166); 1916 TestImpl(xmm15, r2, 166);
1907 1917
1908 #undef TestImpl 1918 #undef TestImpl
1909 } 1919 }
1910 1920
1911 } // end of anonymous namespace 1921 } // end of anonymous namespace
1912 } // end of namespace Test 1922 } // end of namespace Test
1913 } // end of namespace X8664 1923 } // end of namespace X8664
1914 } // end of namespace Ice 1924 } // end of namespace Ice
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