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| 1 //===- subzero/unittest/AssemblerX8664/DataMov.cpp ------------------------===// | 1 //===- subzero/unittest/AssemblerX8664/DataMov.cpp ------------------------===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 #include "AssemblerX8664/TestUtil.h" | 9 #include "AssemblerX8664/TestUtil.h" |
| 10 | 10 |
| (...skipping 245 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 256 TestImpl(r11); | 256 TestImpl(r11); |
| 257 TestImpl(r12); | 257 TestImpl(r12); |
| 258 TestImpl(r13); | 258 TestImpl(r13); |
| 259 TestImpl(r14); | 259 TestImpl(r14); |
| 260 TestImpl(r15); | 260 TestImpl(r15); |
| 261 | 261 |
| 262 #undef TestImpl | 262 #undef TestImpl |
| 263 #undef TestRegAddr | 263 #undef TestRegAddr |
| 264 } | 264 } |
| 265 | 265 |
| 266 TEST_F(AssemblerX8664Test, Movabs) { |
| 267 #define TestImplValue(Dst, Value) \ |
| 268 do { \ |
| 269 static constexpr char TestString[] = "(" #Dst ", " #Value ")"; \ |
| 270 uint64_t V = (Value); \ |
| 271 __ movabs(Encoded_GPR_##Dst##q(), V); \ |
| 272 \ |
| 273 AssembledTest test = assemble(); \ |
| 274 \ |
| 275 test.run(); \ |
| 276 \ |
| 277 ASSERT_EQ(V, test.DST()) << TestString; \ |
| 278 } while (0) |
| 279 |
| 280 #define TestImpl(Dst) \ |
| 281 do { \ |
| 282 for (uint64_t V = {0, 1, 0xFFFFFFull, 0x80000000ull, \ |
| 283 0xFFFFFFFFFFFFFFFFull}) { \ |
| 284 TestImpl(Dst, V); \ |
| 285 } \ |
| 286 } while (0) |
| 287 |
| 288 #undef TestImpl |
| 289 #undef TestImplValue |
| 290 } |
| 291 |
| 266 TEST_F(AssemblerX8664Test, Movzx) { | 292 TEST_F(AssemblerX8664Test, Movzx) { |
| 267 static constexpr uint32_t Mask8 = 0x000000FF; | 293 static constexpr uint32_t Mask8 = 0x000000FF; |
| 268 static constexpr uint32_t Mask16 = 0x0000FFFF; | 294 static constexpr uint32_t Mask16 = 0x0000FFFF; |
| 269 | 295 |
| 270 #define TestImplRegReg(Dst, Src, Suffix, Size) \ | 296 #define TestImplRegReg(Dst, Src, Suffix, Size) \ |
| 271 do { \ | 297 do { \ |
| 272 const uint32_t T0 = allocateDqword(); \ | 298 const uint32_t T0 = allocateDqword(); \ |
| 273 static constexpr uint64_t V0 = 0xAAAAAAAAAAAAAAAAull; \ | 299 static constexpr uint64_t V0 = 0xAAAAAAAAAAAAAAAAull; \ |
| 274 static constexpr uint32_t Value = (0xBEEF) & Mask##Size; \ | 300 static constexpr uint32_t Value = (0xBEEF) & Mask##Size; \ |
| 275 __ mov(IceType_i64, Encoded_GPR_##Dst##q(), dwordAddress(T0)); \ | 301 __ mov(IceType_i64, Encoded_GPR_##Dst##q(), dwordAddress(T0)); \ |
| (...skipping 394 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 670 } while (0) | 696 } while (0) |
| 671 | 697 |
| 672 TestMovssXmmXmm(32); | 698 TestMovssXmmXmm(32); |
| 673 TestMovssXmmXmm(64); | 699 TestMovssXmmXmm(64); |
| 674 | 700 |
| 675 #undef TestMovssXmmXmm | 701 #undef TestMovssXmmXmm |
| 676 #undef TestMovssXmmXmmType | 702 #undef TestMovssXmmXmmType |
| 677 } | 703 } |
| 678 | 704 |
| 679 TEST_F(AssemblerX8664Test, MovdToXmm) { | 705 TEST_F(AssemblerX8664Test, MovdToXmm) { |
| 680 #define TestMovdXmmReg(Src, Dst, Value) \ | 706 #define TestMovdXmmReg32(Src, Dst, Value) \ |
| 681 do { \ | 707 do { \ |
| 682 assert(((Value)&0xFFFFFFFF) == (Value)); \ | 708 assert(((Value)&0xFFFFFFFF) == (Value)); \ |
| 683 static constexpr char TestString[] = "(" #Src ", " #Dst ")"; \ | 709 static constexpr char TestString[] = "(" #Src ", " #Dst ")"; \ |
| 684 const uint32_t T0 = allocateQword(); \ | 710 const uint32_t T0 = allocateQword(); \ |
| 685 const uint64_t V0 = 0xFFFFFFFF00000000ull; \ | 711 const uint64_t V0 = 0xFFFFFFFF00000000ull; \ |
| 686 \ | 712 \ |
| 687 __ mov(IceType_i32, Encoded_GPR_##Src(), Immediate(Value)); \ | 713 __ mov(IceType_i32, Encoded_GPR_##Src(), Immediate(Value)); \ |
| 688 __ movss(IceType_f64, Encoded_Xmm_##Dst(), dwordAddress(T0)); \ | 714 __ movss(IceType_f64, Encoded_Xmm_##Dst(), dwordAddress(T0)); \ |
| 689 __ movd(Encoded_Xmm_##Dst(), Encoded_GPR_##Src()); \ | 715 __ movd(IceType_i32, Encoded_Xmm_##Dst(), Encoded_GPR_##Src()); \ |
| 690 \ | 716 \ |
| 691 AssembledTest test = assemble(); \ | 717 AssembledTest test = assemble(); \ |
| 692 \ | 718 \ |
| 693 test.setQwordTo(T0, V0); \ | 719 test.setQwordTo(T0, V0); \ |
| 694 test.run(); \ | 720 test.run(); \ |
| 695 \ | 721 \ |
| 696 ASSERT_EQ(Value, test.Dst<uint64_t>()) << TestString << " value is " \ | 722 ASSERT_EQ(Value, test.Dst<uint64_t>()) << TestString << " value is " \ |
| 697 << Value; \ | 723 << Value; \ |
| 698 reset(); \ | 724 reset(); \ |
| 699 } while (0) | 725 } while (0) |
| 700 | 726 |
| 701 #define TestMovdXmmAddr(Dst, Value) \ | 727 #define TestMovdXmmReg64(Src, Dst, Value) \ |
| 728 do { \ |
| 729 assert(((Value)&0xFFFFFFFF) == (Value)); \ |
| 730 static constexpr char TestString[] = "(" #Src ", " #Dst ")"; \ |
| 731 const uint32_t T0 = allocateQword(); \ |
| 732 const uint64_t V0 = 0xFFFFFFFF00000000ull; \ |
| 733 const uint64_t Expected = (static_cast<uint64_t>(Value) << 32) | (Value); \ |
| 734 \ |
| 735 __ movabs(Encoded_GPR_##Src(), Expected); \ |
| 736 __ movss(IceType_f64, Encoded_Xmm_##Dst(), dwordAddress(T0)); \ |
| 737 __ movd(IceType_i64, Encoded_Xmm_##Dst(), Encoded_GPR_##Src()); \ |
| 738 \ |
| 739 AssembledTest test = assemble(); \ |
| 740 \ |
| 741 test.setQwordTo(T0, V0); \ |
| 742 test.run(); \ |
| 743 \ |
| 744 ASSERT_EQ(Expected, test.Dst<uint64_t>()) << TestString << " value is " \ |
| 745 << Value; \ |
| 746 reset(); \ |
| 747 } while (0) |
| 748 |
| 749 #define TestMovdXmmReg(Src, Dst, Value) \ |
| 750 do { \ |
| 751 TestMovdXmmReg32(Src, Dst, Value); \ |
| 752 TestMovdXmmReg64(Src, Dst, Value); \ |
| 753 } while (0) |
| 754 |
| 755 #define TestMovdXmmAddr32(Dst, Value) \ |
| 702 do { \ | 756 do { \ |
| 703 assert(((Value)&0xFFFFFFFF) == (Value)); \ | 757 assert(((Value)&0xFFFFFFFF) == (Value)); \ |
| 704 static constexpr char TestString[] = "(" #Dst ", Addr)"; \ | 758 static constexpr char TestString[] = "(" #Dst ", Addr)"; \ |
| 705 const uint32_t T0 = allocateQword(); \ | 759 const uint32_t T0 = allocateQword(); \ |
| 706 const uint32_t V0 = Value; \ | 760 const uint32_t V0 = Value; \ |
| 707 const uint32_t T1 = allocateQword(); \ | 761 const uint32_t T1 = allocateQword(); \ |
| 708 const uint64_t V1 = 0xFFFFFFFF00000000ull; \ | 762 const uint64_t V1 = 0xFFFFFFFF00000000ull; \ |
| 709 \ | 763 \ |
| 710 __ movss(IceType_f64, Encoded_Xmm_##Dst(), dwordAddress(T1)); \ | 764 __ movss(IceType_f64, Encoded_Xmm_##Dst(), dwordAddress(T1)); \ |
| 711 __ movd(Encoded_Xmm_##Dst(), dwordAddress(T0)); \ | 765 __ movd(IceType_i32, Encoded_Xmm_##Dst(), dwordAddress(T0)); \ |
| 712 \ | 766 \ |
| 713 AssembledTest test = assemble(); \ | 767 AssembledTest test = assemble(); \ |
| 714 \ | 768 \ |
| 715 test.setDwordTo(T0, V0); \ | 769 test.setDwordTo(T0, V0); \ |
| 716 test.setQwordTo(T1, V1); \ | 770 test.setQwordTo(T1, V1); \ |
| 717 test.run(); \ | 771 test.run(); \ |
| 718 \ | 772 \ |
| 719 ASSERT_EQ(Value, test.Dst<uint64_t>()) << TestString << " value is " \ | 773 ASSERT_EQ(Value, test.Dst<uint64_t>()) << TestString << " value is " \ |
| 720 << Value; \ | 774 << Value; \ |
| 721 reset(); \ | 775 reset(); \ |
| 722 } while (0) | 776 } while (0) |
| 723 | 777 |
| 778 #define TestMovdXmmAddr64(Dst, Value) \ |
| 779 do { \ |
| 780 assert(((Value)&0xFFFFFFFF) == (Value)); \ |
| 781 static constexpr char TestString[] = "(" #Dst ", Addr)"; \ |
| 782 const uint32_t T0 = allocateQword(); \ |
| 783 const uint32_t V0 = (static_cast<uint64_t>(Value) << 32) | (Value); \ |
| 784 const uint32_t T1 = allocateQword(); \ |
| 785 const uint64_t V1 = 0xFFFFFFFF00000000ull; \ |
| 786 \ |
| 787 __ movss(IceType_f64, Encoded_Xmm_##Dst(), dwordAddress(T1)); \ |
| 788 __ movd(IceType_i64, Encoded_Xmm_##Dst(), dwordAddress(T0)); \ |
| 789 \ |
| 790 AssembledTest test = assemble(); \ |
| 791 \ |
| 792 test.setDwordTo(T0, V0); \ |
| 793 test.setQwordTo(T1, V1); \ |
| 794 test.run(); \ |
| 795 \ |
| 796 ASSERT_EQ(Value, test.Dst<uint64_t>()) << TestString << " value is " \ |
| 797 << Value; \ |
| 798 reset(); \ |
| 799 } while (0) |
| 800 |
| 801 #define TestMovdXmmAddr(Dst, Value) \ |
| 802 do { \ |
| 803 TestMovdXmmAddr32(Dst, Value); \ |
| 804 TestMovdXmmAddr64(Dst, Value); \ |
| 805 } while (0) |
| 806 |
| 724 #define TestMovd(Dst) \ | 807 #define TestMovd(Dst) \ |
| 725 do { \ | 808 do { \ |
| 726 for (uint32_t Value : {0u, 1u, 0x7FFFFFFFu, 0x80000000u, 0xFFFFFFFFu}) { \ | 809 for (uint32_t Value : {0u, 1u, 0x7FFFFFFFu, 0x80000000u, 0xFFFFFFFFu}) { \ |
| 727 TestMovdXmmReg(r1, Dst, Value); \ | 810 TestMovdXmmReg(r1, Dst, Value); \ |
| 728 TestMovdXmmReg(r2, Dst, Value); \ | 811 TestMovdXmmReg(r2, Dst, Value); \ |
| 729 TestMovdXmmReg(r3, Dst, Value); \ | 812 TestMovdXmmReg(r3, Dst, Value); \ |
| 730 TestMovdXmmReg(r4, Dst, Value); \ | 813 TestMovdXmmReg(r4, Dst, Value); \ |
| 731 TestMovdXmmReg(r5, Dst, Value); \ | 814 TestMovdXmmReg(r5, Dst, Value); \ |
| 732 TestMovdXmmReg(r6, Dst, Value); \ | 815 TestMovdXmmReg(r6, Dst, Value); \ |
| 733 TestMovdXmmReg(r7, Dst, Value); \ | 816 TestMovdXmmReg(r7, Dst, Value); \ |
| (...skipping 18 matching lines...) Expand all Loading... |
| 752 TestMovd(xmm7); | 835 TestMovd(xmm7); |
| 753 TestMovd(xmm8); | 836 TestMovd(xmm8); |
| 754 TestMovd(xmm9); | 837 TestMovd(xmm9); |
| 755 TestMovd(xmm10); | 838 TestMovd(xmm10); |
| 756 TestMovd(xmm11); | 839 TestMovd(xmm11); |
| 757 TestMovd(xmm12); | 840 TestMovd(xmm12); |
| 758 TestMovd(xmm13); | 841 TestMovd(xmm13); |
| 759 TestMovd(xmm14); | 842 TestMovd(xmm14); |
| 760 TestMovd(xmm15); | 843 TestMovd(xmm15); |
| 761 | 844 |
| 845 #undef TestMovd |
| 762 #undef TestMovdXmmAddr | 846 #undef TestMovdXmmAddr |
| 847 #undef TestMovdXmmAddr64 |
| 848 #undef TestMovdXmmAddr32 |
| 763 #undef TestMovdXmmReg | 849 #undef TestMovdXmmReg |
| 764 #undef TestMovd | 850 #undef TestMovdXmmReg64 |
| 851 #undef TestMovdXmmReg32 |
| 765 } | 852 } |
| 766 | 853 |
| 767 TEST_F(AssemblerX8664Test, MovdFromXmm) { | 854 TEST_F(AssemblerX8664Test, MovdFromXmm) { |
| 768 #define TestMovdRegXmm(Src, Dst, Value) \ | 855 #define TestMovdRegXmm32(Src, Dst, Value) \ |
| 769 do { \ | 856 do { \ |
| 770 assert(((Value)&0xFFFFFFFF) == (Value)); \ | 857 assert(((Value)&0xFFFFFFFF) == (Value)); \ |
| 771 static constexpr char TestString[] = "(" #Src ", " #Dst ")"; \ | 858 static constexpr char TestString[] = "(" #Src ", " #Dst ")"; \ |
| 772 const uint32_t T0 = allocateDword(); \ | 859 const uint32_t T0 = allocateDword(); \ |
| 773 const uint32_t V0 = Value; \ | 860 const uint32_t V0 = Value; \ |
| 774 \ | 861 \ |
| 775 __ movss(IceType_f64, Encoded_Xmm_##Src(), dwordAddress(T0)); \ | 862 __ movss(IceType_f64, Encoded_Xmm_##Src(), dwordAddress(T0)); \ |
| 776 __ movd(Encoded_GPR_##Dst(), Encoded_Xmm_##Src()); \ | 863 __ movd(IceType_i32, Encoded_GPR_##Dst(), Encoded_Xmm_##Src()); \ |
| 777 \ | 864 \ |
| 778 AssembledTest test = assemble(); \ | 865 AssembledTest test = assemble(); \ |
| 779 \ | 866 \ |
| 780 test.setDwordTo(T0, V0); \ | 867 test.setDwordTo(T0, V0); \ |
| 781 test.run(); \ | 868 test.run(); \ |
| 782 \ | 869 \ |
| 783 ASSERT_EQ(Value, test.contentsOfDword(T0)) << TestString << " value is " \ | 870 ASSERT_EQ(Value, test.contentsOfDword(T0)) << TestString << " value is " \ |
| 784 << Value; \ | 871 << Value; \ |
| 785 reset(); \ | 872 reset(); \ |
| 786 } while (0) | 873 } while (0) |
| 787 | 874 |
| 788 #define TestMovdAddrXmm(Src, Value) \ | 875 #define TestMovdRegXmm64(Src, Dst, Value) \ |
| 876 do { \ |
| 877 assert(((Value)&0xFFFFFFFF) == (Value)); \ |
| 878 static constexpr char TestString[] = "(" #Src ", " #Dst ")"; \ |
| 879 const uint32_t T0 = allocateDword(); \ |
| 880 const uint64_t V0 = (static_cast<uint64_t>(Value) << 32) | (Value); \ |
| 881 \ |
| 882 __ movss(IceType_f64, Encoded_Xmm_##Src(), dwordAddress(T0)); \ |
| 883 __ movd(IceType_i64, Encoded_GPR_##Dst(), Encoded_Xmm_##Src()); \ |
| 884 \ |
| 885 AssembledTest test = assemble(); \ |
| 886 \ |
| 887 test.setQwordTo(T0, V0); \ |
| 888 test.run(); \ |
| 889 \ |
| 890 ASSERT_EQ(V0, test.contentsOfQword(T0)) << TestString << " value is " \ |
| 891 << Value; \ |
| 892 reset(); \ |
| 893 } while (0) |
| 894 |
| 895 #define TestMovdRegXmm(Src, Dst, Value) \ |
| 896 do { \ |
| 897 TestMovdRegXmm32(Src, Dst, Value); \ |
| 898 TestMovdRegXmm64(Src, Dst, Value); \ |
| 899 } while (0) |
| 900 |
| 901 #define TestMovdAddrXmm32(Src, Value) \ |
| 789 do { \ | 902 do { \ |
| 790 assert(((Value)&0xFFFFFFFF) == (Value)); \ | 903 assert(((Value)&0xFFFFFFFF) == (Value)); \ |
| 791 static constexpr char TestString[] = "(" #Src ", Addr)"; \ | 904 static constexpr char TestString[] = "(" #Src ", Addr)"; \ |
| 792 const uint32_t T0 = allocateDword(); \ | 905 const uint32_t T0 = allocateDword(); \ |
| 793 const uint32_t V0 = Value; \ | 906 const uint32_t V0 = Value; \ |
| 794 const uint32_t T1 = allocateDword(); \ | 907 const uint32_t T1 = allocateDword(); \ |
| 795 const uint32_t V1 = ~(Value); \ | 908 const uint32_t V1 = ~(Value); \ |
| 796 \ | 909 \ |
| 797 __ movss(IceType_f64, Encoded_Xmm_##Src(), dwordAddress(T0)); \ | 910 __ movss(IceType_f64, Encoded_Xmm_##Src(), dwordAddress(T0)); \ |
| 798 __ movd(dwordAddress(T1), Encoded_Xmm_##Src()); \ | 911 __ movd(IceType_i32, dwordAddress(T1), Encoded_Xmm_##Src()); \ |
| 799 \ | 912 \ |
| 800 AssembledTest test = assemble(); \ | 913 AssembledTest test = assemble(); \ |
| 801 \ | 914 \ |
| 802 test.setDwordTo(T0, V0); \ | 915 test.setDwordTo(T0, V0); \ |
| 803 test.setDwordTo(T1, V1); \ | 916 test.setDwordTo(T1, V1); \ |
| 804 test.run(); \ | 917 test.run(); \ |
| 805 \ | 918 \ |
| 806 ASSERT_EQ(Value, test.contentsOfDword(T1)) << TestString << " value is " \ | 919 ASSERT_EQ(Value, test.contentsOfDword(T1)) << TestString << " value is " \ |
| 807 << Value; \ | 920 << Value; \ |
| 808 reset(); \ | 921 reset(); \ |
| 809 } while (0) | 922 } while (0) |
| 810 | 923 |
| 924 #define TestMovdAddrXmm64(Src, Value) \ |
| 925 do { \ |
| 926 assert(((Value)&0xFFFFFFFF) == (Value)); \ |
| 927 static constexpr char TestString[] = "(" #Src ", Addr)"; \ |
| 928 const uint32_t T0 = allocateQword(); \ |
| 929 const uint64_t V0 = (static_cast<uint64_t>(Value) << 32) | Value; \ |
| 930 const uint32_t T1 = allocateQword(); \ |
| 931 const uint64_t V1 = ~V0; \ |
| 932 \ |
| 933 __ movss(IceType_f64, Encoded_Xmm_##Src(), dwordAddress(T0)); \ |
| 934 __ movd(IceType_i64, dwordAddress(T1), Encoded_Xmm_##Src()); \ |
| 935 \ |
| 936 AssembledTest test = assemble(); \ |
| 937 \ |
| 938 test.setQwordTo(T0, V0); \ |
| 939 test.setQwordTo(T1, V1); \ |
| 940 test.run(); \ |
| 941 \ |
| 942 ASSERT_EQ(V0, test.contentsOfQword(T1)) << TestString << " value is " \ |
| 943 << Value; \ |
| 944 reset(); \ |
| 945 } while (0) |
| 946 |
| 947 #define TestMovdAddrXmm(Src, Value) \ |
| 948 do { \ |
| 949 TestMovdAddrXmm32(Src, Value); \ |
| 950 TestMovdAddrXmm64(Src, Value); \ |
| 951 } while (0) |
| 952 |
| 811 #define TestMovd(Src) \ | 953 #define TestMovd(Src) \ |
| 812 do { \ | 954 do { \ |
| 813 for (uint32_t Value : {0u, 1u, 0x7FFFFFFFu, 0x80000000u, 0xFFFFFFFFu}) { \ | 955 for (uint32_t Value : {0u, 1u, 0x7FFFFFFFu, 0x80000000u, 0xFFFFFFFFu}) { \ |
| 814 TestMovdRegXmm(Src, r1, Value); \ | 956 TestMovdRegXmm(Src, r1, Value); \ |
| 815 TestMovdRegXmm(Src, r2, Value); \ | 957 TestMovdRegXmm(Src, r2, Value); \ |
| 816 TestMovdRegXmm(Src, r3, Value); \ | 958 TestMovdRegXmm(Src, r3, Value); \ |
| 817 TestMovdRegXmm(Src, r4, Value); \ | 959 TestMovdRegXmm(Src, r4, Value); \ |
| 818 TestMovdRegXmm(Src, r5, Value); \ | 960 TestMovdRegXmm(Src, r5, Value); \ |
| 819 TestMovdRegXmm(Src, r6, Value); \ | 961 TestMovdRegXmm(Src, r6, Value); \ |
| 820 TestMovdRegXmm(Src, r7, Value); \ | 962 TestMovdRegXmm(Src, r7, Value); \ |
| (...skipping 18 matching lines...) Expand all Loading... |
| 839 TestMovd(xmm7); | 981 TestMovd(xmm7); |
| 840 TestMovd(xmm8); | 982 TestMovd(xmm8); |
| 841 TestMovd(xmm9); | 983 TestMovd(xmm9); |
| 842 TestMovd(xmm10); | 984 TestMovd(xmm10); |
| 843 TestMovd(xmm11); | 985 TestMovd(xmm11); |
| 844 TestMovd(xmm12); | 986 TestMovd(xmm12); |
| 845 TestMovd(xmm13); | 987 TestMovd(xmm13); |
| 846 TestMovd(xmm14); | 988 TestMovd(xmm14); |
| 847 TestMovd(xmm15); | 989 TestMovd(xmm15); |
| 848 | 990 |
| 991 #undef TestMovd |
| 849 #undef TestMovdAddrXmm | 992 #undef TestMovdAddrXmm |
| 993 #undef TestMovdAddrXmm64 |
| 994 #undef TestMovdAddrXmm32 |
| 850 #undef TestMovdRegXmm | 995 #undef TestMovdRegXmm |
| 851 #undef TestMovd | 996 #undef TestMovdRegXmm64 |
| 997 #undef TestMovdRegXmm32 |
| 852 } | 998 } |
| 853 | 999 |
| 854 TEST_F(AssemblerX8664Test, MovqXmmAddr) { | 1000 TEST_F(AssemblerX8664Test, MovqXmmAddr) { |
| 855 #define TestMovd(Dst, Value) \ | 1001 #define TestMovd(Dst, Value) \ |
| 856 do { \ | 1002 do { \ |
| 857 static constexpr char TestString[] = "(" #Dst ", Addr)"; \ | 1003 static constexpr char TestString[] = "(" #Dst ", Addr)"; \ |
| 858 const uint32_t T0 = allocateQword(); \ | 1004 const uint32_t T0 = allocateQword(); \ |
| 859 const uint64_t V0 = Value; \ | 1005 const uint64_t V0 = Value; \ |
| 860 const uint32_t T1 = allocateQword(); \ | 1006 const uint32_t T1 = allocateQword(); \ |
| 861 const uint64_t V1 = ~(Value); \ | 1007 const uint64_t V1 = ~(Value); \ |
| (...skipping 443 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 1305 TestPmovsxdq(xmm15, xmm0); | 1451 TestPmovsxdq(xmm15, xmm0); |
| 1306 | 1452 |
| 1307 #undef TestPmovsxdq | 1453 #undef TestPmovsxdq |
| 1308 #undef TestPmovsxdqXmmXmm | 1454 #undef TestPmovsxdqXmmXmm |
| 1309 } | 1455 } |
| 1310 | 1456 |
| 1311 } // end of anonymous namespace | 1457 } // end of anonymous namespace |
| 1312 } // end of namespace Test | 1458 } // end of namespace Test |
| 1313 } // end of namespace X8664 | 1459 } // end of namespace X8664 |
| 1314 } // end of namespace Ice | 1460 } // end of namespace Ice |
| OLD | NEW |
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Chromium Code Reviews
Issue 1273153002:
Subzero. Native 64-bit int arithmetic on x86-64. (Closed)
Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master