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Side by Side Diff: unittest/AssemblerX8632/XmmArith.cpp

Issue 1273153002: Subzero. Native 64-bit int arithmetic on x86-64. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fixes tests & make format Created 5 years, 4 months ago
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1 //===- subzero/unittest/AssemblerX8632/XmmArith.cpp -----------------------===// 1 //===- subzero/unittest/AssemblerX8632/XmmArith.cpp -----------------------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 #include "AssemblerX8632/TestUtil.h" 9 #include "AssemblerX8632/TestUtil.h"
10 10
(...skipping 1054 matching lines...) Expand 10 before | Expand all | Expand 10 after
1065 1065
1066 #define TestImplSXmmReg(Dst, GPR, Inst, Size) \ 1066 #define TestImplSXmmReg(Dst, GPR, Inst, Size) \
1067 do { \ 1067 do { \
1068 static constexpr char TestString[] = \ 1068 static constexpr char TestString[] = \
1069 "(" #Dst ", " #GPR ", cvt" #Inst ", f" #Size ")"; \ 1069 "(" #Dst ", " #GPR ", cvt" #Inst ", f" #Size ")"; \
1070 const uint32_t T0 = allocateDqword(); \ 1070 const uint32_t T0 = allocateDqword(); \
1071 \ 1071 \
1072 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \ 1072 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \
1073 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##GPR, \ 1073 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##GPR, \
1074 Immediate(Inst##Size##SrcValue)); \ 1074 Immediate(Inst##Size##SrcValue)); \
1075 __ cvt##Inst(IceType_f##Size, XmmRegister::Encoded_Reg_##Dst, \ 1075 __ cvt##Inst(IceType_f##Size, XmmRegister::Encoded_Reg_##Dst, IceType_i32, \
1076 GPRRegister::Encoded_Reg_##GPR); \ 1076 GPRRegister::Encoded_Reg_##GPR); \
1077 \ 1077 \
1078 AssembledTest test = assemble(); \ 1078 AssembledTest test = assemble(); \
1079 test.setDqwordTo(T0, Inst##Size##DstValue); \ 1079 test.setDqwordTo(T0, Inst##Size##DstValue); \
1080 test.run(); \ 1080 test.run(); \
1081 \ 1081 \
1082 ASSERT_EQ(Inst##Size##Expected, test.Dst<Dqword>()) << TestString; \ 1082 ASSERT_EQ(Inst##Size##Expected, test.Dst<Dqword>()) << TestString; \
1083 reset(); \ 1083 reset(); \
1084 } while (0) 1084 } while (0)
1085 1085
1086 #define TestImplSRegXmm(GPR, Src, Inst, Size) \ 1086 #define TestImplSRegXmm(GPR, Src, Inst, Size) \
1087 do { \ 1087 do { \
1088 static constexpr char TestString[] = \ 1088 static constexpr char TestString[] = \
1089 "(" #GPR ", " #Src ", cvt" #Inst ", f" #Size ")"; \ 1089 "(" #GPR ", " #Src ", cvt" #Inst ", f" #Size ")"; \
1090 const uint32_t T0 = allocateDqword(); \ 1090 const uint32_t T0 = allocateDqword(); \
1091 \ 1091 \
1092 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##GPR, \ 1092 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##GPR, \
1093 Immediate(Inst##Size##DstValue)); \ 1093 Immediate(Inst##Size##DstValue)); \
1094 __ movups(XmmRegister::Encoded_Reg_##Src, dwordAddress(T0)); \ 1094 __ movups(XmmRegister::Encoded_Reg_##Src, dwordAddress(T0)); \
1095 __ cvt##Inst(IceType_f##Size, GPRRegister::Encoded_Reg_##GPR, \ 1095 __ cvt##Inst(IceType_i32, GPRRegister::Encoded_Reg_##GPR, IceType_f##Size, \
1096 XmmRegister::Encoded_Reg_##Src); \ 1096 XmmRegister::Encoded_Reg_##Src); \
1097 \ 1097 \
1098 AssembledTest test = assemble(); \ 1098 AssembledTest test = assemble(); \
1099 test.setDqwordTo(T0, Inst##Size##SrcValue); \ 1099 test.setDqwordTo(T0, Inst##Size##SrcValue); \
1100 test.run(); \ 1100 test.run(); \
1101 \ 1101 \
1102 ASSERT_EQ(static_cast<uint32_t>(Inst##Size##Expected), test.GPR()) \ 1102 ASSERT_EQ(static_cast<uint32_t>(Inst##Size##Expected), test.GPR()) \
1103 << TestString; \ 1103 << TestString; \
1104 reset(); \ 1104 reset(); \
1105 } while (0) 1105 } while (0)
(...skipping 19 matching lines...) Expand all
1125 } while (0) 1125 } while (0)
1126 1126
1127 #define TestImplSXmmAddr(Dst, Inst, Size) \ 1127 #define TestImplSXmmAddr(Dst, Inst, Size) \
1128 do { \ 1128 do { \
1129 static constexpr char TestString[] = \ 1129 static constexpr char TestString[] = \
1130 "(" #Dst ", Addr, cvt" #Inst ", f" #Size ")"; \ 1130 "(" #Dst ", Addr, cvt" #Inst ", f" #Size ")"; \
1131 const uint32_t T0 = allocateDqword(); \ 1131 const uint32_t T0 = allocateDqword(); \
1132 const uint32_t T1 = allocateDword(); \ 1132 const uint32_t T1 = allocateDword(); \
1133 \ 1133 \
1134 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \ 1134 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \
1135 __ cvt##Inst(IceType_f##Size, XmmRegister::Encoded_Reg_##Dst, \ 1135 __ cvt##Inst(IceType_f##Size, XmmRegister::Encoded_Reg_##Dst, IceType_i32, \
1136 dwordAddress(T1)); \ 1136 dwordAddress(T1)); \
1137 \ 1137 \
1138 AssembledTest test = assemble(); \ 1138 AssembledTest test = assemble(); \
1139 test.setDqwordTo(T0, Inst##Size##DstValue); \ 1139 test.setDqwordTo(T0, Inst##Size##DstValue); \
1140 test.setDwordTo(T1, Inst##Size##SrcValue); \ 1140 test.setDwordTo(T1, Inst##Size##SrcValue); \
1141 test.run(); \ 1141 test.run(); \
1142 \ 1142 \
1143 ASSERT_EQ(Inst##Size##Expected, test.Dst<Dqword>()) << TestString; \ 1143 ASSERT_EQ(Inst##Size##Expected, test.Dst<Dqword>()) << TestString; \
1144 reset(); \ 1144 reset(); \
1145 } while (0) 1145 } while (0)
1146 1146
1147 #define TestImplSRegAddr(GPR, Inst, Size) \ 1147 #define TestImplSRegAddr(GPR, Inst, Size) \
1148 do { \ 1148 do { \
1149 static constexpr char TestString[] = \ 1149 static constexpr char TestString[] = \
1150 "(" #GPR ", Addr, cvt" #Inst ", f" #Size ")"; \ 1150 "(" #GPR ", Addr, cvt" #Inst ", f" #Size ")"; \
1151 const uint32_t T0 = allocateDqword(); \ 1151 const uint32_t T0 = allocateDqword(); \
1152 \ 1152 \
1153 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##GPR, \ 1153 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##GPR, \
1154 Immediate(Inst##Size##DstValue)); \ 1154 Immediate(Inst##Size##DstValue)); \
1155 __ cvt##Inst(IceType_f##Size, GPRRegister::Encoded_Reg_##GPR, \ 1155 __ cvt##Inst(IceType_i32, GPRRegister::Encoded_Reg_##GPR, IceType_f##Size, \
1156 dwordAddress(T0)); \ 1156 dwordAddress(T0)); \
1157 \ 1157 \
1158 AssembledTest test = assemble(); \ 1158 AssembledTest test = assemble(); \
1159 test.setDqwordTo(T0, Inst##Size##SrcValue); \ 1159 test.setDqwordTo(T0, Inst##Size##SrcValue); \
1160 test.run(); \ 1160 test.run(); \
1161 \ 1161 \
1162 ASSERT_EQ(static_cast<uint32_t>(Inst##Size##Expected), test.GPR()) \ 1162 ASSERT_EQ(static_cast<uint32_t>(Inst##Size##Expected), test.GPR()) \
1163 << TestString; \ 1163 << TestString; \
1164 reset(); \ 1164 reset(); \
1165 } while (0) 1165 } while (0)
(...skipping 641 matching lines...) Expand 10 before | Expand all | Expand 10 after
1807 TestImpl(xmm6, ebx, 7); 1807 TestImpl(xmm6, ebx, 7);
1808 TestImpl(xmm7, ecx, 8); 1808 TestImpl(xmm7, ecx, 8);
1809 1809
1810 #undef TestImpl 1810 #undef TestImpl
1811 } 1811 }
1812 1812
1813 } // end of anonymous namespace 1813 } // end of anonymous namespace
1814 } // end of namespace Test 1814 } // end of namespace Test
1815 } // end of namespace X8632 1815 } // end of namespace X8632
1816 } // end of namespace Ice 1816 } // end of namespace Ice
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