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Issue 1273153002: Subzero. Native 64-bit int arithmetic on x86-64. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fixes tests & make format Created 5 years, 4 months ago
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1 //===- subzero/unittest/AssemblerX8632/DataMov.cpp ------------------------===// 1 //===- subzero/unittest/AssemblerX8632/DataMov.cpp ------------------------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 #include "AssemblerX8632/TestUtil.h" 9 #include "AssemblerX8632/TestUtil.h"
10 10
(...skipping 520 matching lines...) Expand 10 before | Expand all | Expand 10 after
531 TEST_F(AssemblerX8632Test, MovdToXmm) { 531 TEST_F(AssemblerX8632Test, MovdToXmm) {
532 #define TestMovdXmmReg(Src, Dst, Value) \ 532 #define TestMovdXmmReg(Src, Dst, Value) \
533 do { \ 533 do { \
534 assert(((Value)&0xFFFFFFFF) == (Value)); \ 534 assert(((Value)&0xFFFFFFFF) == (Value)); \
535 static constexpr char TestString[] = "(" #Src ", " #Dst ")"; \ 535 static constexpr char TestString[] = "(" #Src ", " #Dst ")"; \
536 const uint32_t T0 = allocateQword(); \ 536 const uint32_t T0 = allocateQword(); \
537 const uint64_t V0 = 0xFFFFFFFF00000000ull; \ 537 const uint64_t V0 = 0xFFFFFFFF00000000ull; \
538 \ 538 \
539 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Src, Immediate(Value)); \ 539 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Src, Immediate(Value)); \
540 __ movss(IceType_f64, XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \ 540 __ movss(IceType_f64, XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \
541 __ movd(XmmRegister::Encoded_Reg_##Dst, GPRRegister::Encoded_Reg_##Src); \ 541 __ movd(IceType_i32, XmmRegister::Encoded_Reg_##Dst, \
542 GPRRegister::Encoded_Reg_##Src); \
542 \ 543 \
543 AssembledTest test = assemble(); \ 544 AssembledTest test = assemble(); \
544 \ 545 \
545 test.setQwordTo(T0, V0); \ 546 test.setQwordTo(T0, V0); \
546 test.run(); \ 547 test.run(); \
547 \ 548 \
548 ASSERT_EQ(Value, test.Dst<uint64_t>()) << TestString << " value is " \ 549 ASSERT_EQ(Value, test.Dst<uint64_t>()) << TestString << " value is " \
549 << Value; \ 550 << Value; \
550 reset(); \ 551 reset(); \
551 } while (0) 552 } while (0)
552 553
553 #define TestMovdXmmAddr(Dst, Value) \ 554 #define TestMovdXmmAddr(Dst, Value) \
554 do { \ 555 do { \
555 assert(((Value)&0xFFFFFFFF) == (Value)); \ 556 assert(((Value)&0xFFFFFFFF) == (Value)); \
556 static constexpr char TestString[] = "(" #Dst ", Addr)"; \ 557 static constexpr char TestString[] = "(" #Dst ", Addr)"; \
557 const uint32_t T0 = allocateQword(); \ 558 const uint32_t T0 = allocateQword(); \
558 const uint32_t V0 = Value; \ 559 const uint32_t V0 = Value; \
559 const uint32_t T1 = allocateQword(); \ 560 const uint32_t T1 = allocateQword(); \
560 const uint64_t V1 = 0xFFFFFFFF00000000ull; \ 561 const uint64_t V1 = 0xFFFFFFFF00000000ull; \
561 \ 562 \
562 __ movss(IceType_f64, XmmRegister::Encoded_Reg_##Dst, dwordAddress(T1)); \ 563 __ movss(IceType_f64, XmmRegister::Encoded_Reg_##Dst, dwordAddress(T1)); \
563 __ movd(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \ 564 __ movd(IceType_i32, XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \
564 \ 565 \
565 AssembledTest test = assemble(); \ 566 AssembledTest test = assemble(); \
566 \ 567 \
567 test.setDwordTo(T0, V0); \ 568 test.setDwordTo(T0, V0); \
568 test.setQwordTo(T1, V1); \ 569 test.setQwordTo(T1, V1); \
569 test.run(); \ 570 test.run(); \
570 \ 571 \
571 ASSERT_EQ(Value, test.Dst<uint64_t>()) << TestString << " value is " \ 572 ASSERT_EQ(Value, test.Dst<uint64_t>()) << TestString << " value is " \
572 << Value; \ 573 << Value; \
573 reset(); \ 574 reset(); \
(...skipping 28 matching lines...) Expand all
602 603
603 TEST_F(AssemblerX8632Test, MovdFromXmm) { 604 TEST_F(AssemblerX8632Test, MovdFromXmm) {
604 #define TestMovdRegXmm(Src, Dst, Value) \ 605 #define TestMovdRegXmm(Src, Dst, Value) \
605 do { \ 606 do { \
606 assert(((Value)&0xFFFFFFFF) == (Value)); \ 607 assert(((Value)&0xFFFFFFFF) == (Value)); \
607 static constexpr char TestString[] = "(" #Src ", " #Dst ")"; \ 608 static constexpr char TestString[] = "(" #Src ", " #Dst ")"; \
608 const uint32_t T0 = allocateDword(); \ 609 const uint32_t T0 = allocateDword(); \
609 const uint32_t V0 = Value; \ 610 const uint32_t V0 = Value; \
610 \ 611 \
611 __ movss(IceType_f64, XmmRegister::Encoded_Reg_##Src, dwordAddress(T0)); \ 612 __ movss(IceType_f64, XmmRegister::Encoded_Reg_##Src, dwordAddress(T0)); \
612 __ movd(GPRRegister::Encoded_Reg_##Dst, XmmRegister::Encoded_Reg_##Src); \ 613 __ movd(IceType_i32, GPRRegister::Encoded_Reg_##Dst, \
614 XmmRegister::Encoded_Reg_##Src); \
613 \ 615 \
614 AssembledTest test = assemble(); \ 616 AssembledTest test = assemble(); \
615 \ 617 \
616 test.setDwordTo(T0, V0); \ 618 test.setDwordTo(T0, V0); \
617 test.run(); \ 619 test.run(); \
618 \ 620 \
619 ASSERT_EQ(Value, test.contentsOfDword(T0)) << TestString << " value is " \ 621 ASSERT_EQ(Value, test.contentsOfDword(T0)) << TestString << " value is " \
620 << Value; \ 622 << Value; \
621 reset(); \ 623 reset(); \
622 } while (0) 624 } while (0)
623 625
624 #define TestMovdAddrXmm(Src, Value) \ 626 #define TestMovdAddrXmm(Src, Value) \
625 do { \ 627 do { \
626 assert(((Value)&0xFFFFFFFF) == (Value)); \ 628 assert(((Value)&0xFFFFFFFF) == (Value)); \
627 static constexpr char TestString[] = "(" #Src ", Addr)"; \ 629 static constexpr char TestString[] = "(" #Src ", Addr)"; \
628 const uint32_t T0 = allocateDword(); \ 630 const uint32_t T0 = allocateDword(); \
629 const uint32_t V0 = Value; \ 631 const uint32_t V0 = Value; \
630 const uint32_t T1 = allocateDword(); \ 632 const uint32_t T1 = allocateDword(); \
631 const uint32_t V1 = ~(Value); \ 633 const uint32_t V1 = ~(Value); \
632 \ 634 \
633 __ movss(IceType_f64, XmmRegister::Encoded_Reg_##Src, dwordAddress(T0)); \ 635 __ movss(IceType_f64, XmmRegister::Encoded_Reg_##Src, dwordAddress(T0)); \
634 __ movd(dwordAddress(T1), XmmRegister::Encoded_Reg_##Src); \ 636 __ movd(IceType_i32, dwordAddress(T1), XmmRegister::Encoded_Reg_##Src); \
635 \ 637 \
636 AssembledTest test = assemble(); \ 638 AssembledTest test = assemble(); \
637 \ 639 \
638 test.setDwordTo(T0, V0); \ 640 test.setDwordTo(T0, V0); \
639 test.setDwordTo(T1, V1); \ 641 test.setDwordTo(T1, V1); \
640 test.run(); \ 642 test.run(); \
641 \ 643 \
642 ASSERT_EQ(Value, test.contentsOfDword(T1)) << TestString << " value is " \ 644 ASSERT_EQ(Value, test.contentsOfDword(T1)) << TestString << " value is " \
643 << Value; \ 645 << Value; \
644 reset(); \ 646 reset(); \
(...skipping 538 matching lines...) Expand 10 before | Expand all | Expand 10 after
1183 TestCmovRegAddr(le, ebx, 0x80000000u, 0x1u, edx, 1u); 1185 TestCmovRegAddr(le, ebx, 0x80000000u, 0x1u, edx, 1u);
1184 TestCmovRegAddr(le, ebx, 0x1u, 0x80000000u, edx, 0u); 1186 TestCmovRegAddr(le, ebx, 0x1u, 0x80000000u, edx, 0u);
1185 1187
1186 #undef TestCmovRegAddr 1188 #undef TestCmovRegAddr
1187 } 1189 }
1188 1190
1189 } // end of anonymous namespace 1191 } // end of anonymous namespace
1190 } // end of namespace Test 1192 } // end of namespace Test
1191 } // end of namespace X8632 1193 } // end of namespace X8632
1192 } // end of namespace Ice 1194 } // end of namespace Ice
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