Subzero. Native 64-bit int arithmetic on x86-64.

src/IceInstX86BaseImpl.h

 //===- subzero/src/IceInstX86BaseImpl.h - Generic X86 instructions -*- C++ -*=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 699 matching lines @@
               ->stackVarToAsmOperand(SrcVar);
       (Asm->*(Emitter.GPRAddr))(Ty, VarReg, SrcStackAddr);
     }
   } else if (const auto Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
     Mem->emitSegmentOverride(Asm);
     (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Mem->toAsmAddress(Asm));
   } else if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.GPRImm))(Ty, VarReg, Immediate(Imm->getValue()));
   } else if (const auto Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
-    AssemblerFixup *Fixup = Asm->createFixup(llvm::ELF::R_386_32, Reloc);
+    AssemblerFixup *Fixup =
+        Asm->createFixup(InstX86Base<Machine>::Traits::RelFixup, Reloc);
     (Asm->*(Emitter.GPRImm))(Ty, VarReg, Immediate(Reloc->getOffset(), Fixup));
   } else if (const auto Split = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::VariableSplit>(Src)) {
     (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Split->toAsmAddress(Func));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
 void emitIASAddrOpTyGPR(
     const Cfg *Func, Type Ty,
     const typename InstX86Base<Machine>::Traits::Address &Addr,
     const Operand *Src,
     const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterAddrOp
         &Emitter) {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   // Src can only be Reg or Immediate.
   if (const auto SrcVar = llvm::dyn_cast<Variable>(Src)) {
     assert(SrcVar->hasReg());
     typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister SrcReg =
         InstX86Base<Machine>::Traits::RegisterSet::getEncodedByteRegOrGPR(
             Ty, SrcVar->getRegNum());
     (Asm->*(Emitter.AddrGPR))(Ty, Addr, SrcReg);
   } else if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
     (Asm->*(Emitter.AddrImm))(Ty, Addr, Immediate(Imm->getValue()));
   } else if (const auto Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
-    AssemblerFixup *Fixup = Asm->createFixup(llvm::ELF::R_386_32, Reloc);
+    AssemblerFixup *Fixup =
+        Asm->createFixup(InstX86Base<Machine>::Traits::RelFixup, Reloc);
     (Asm->*(Emitter.AddrImm))(Ty, Addr, Immediate(Reloc->getOffset(), Fixup));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine>
 void emitIASAsAddrOpTyGPR(
     const Cfg *Func, Type Ty, const Operand *Op0, const Operand *Op1,
     const typename InstX86Base<Machine>::Traits::Assembler::GPREmitterAddrOp
@@ skipping 150 matching lines @@
     (Asm->*(Emitter.XmmAddr))(
         Ty, VarReg,
         InstX86Base<Machine>::Traits::Address::ofConstPool(Asm, Imm));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine, typename DReg_t, typename SReg_t,
           DReg_t (*destEnc)(int32_t), SReg_t (*srcEnc)(int32_t)>
-void emitIASCastRegOp(const Cfg *Func, Type DispatchTy, const Variable *Dest,
-                      const Operand *Src,
+void emitIASCastRegOp(const Cfg *Func, Type DestTy, const Variable *Dest,
+                      Type SrcTy, const Operand *Src,
                       const typename InstX86Base<Machine>::Traits::Assembler::
                           template CastEmitterRegOp<DReg_t, SReg_t> &Emitter) {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(Dest->hasReg());
   DReg_t DestReg = destEnc(Dest->getRegNum());
   if (const auto SrcVar = llvm::dyn_cast<Variable>(Src)) {
     if (SrcVar->hasReg()) {
       SReg_t SrcReg = srcEnc(SrcVar->getRegNum());
-      (Asm->*(Emitter.RegReg))(DispatchTy, DestReg, SrcReg);
+      (Asm->*(Emitter.RegReg))(DestTy, DestReg, SrcTy, SrcReg);
     } else {
       typename InstX86Base<Machine>::Traits::Address SrcStackAddr =
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
               Func->getTarget())
               ->stackVarToAsmOperand(SrcVar);
-      (Asm->*(Emitter.RegAddr))(DispatchTy, DestReg, SrcStackAddr);
+      (Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy, SrcStackAddr);
     }
   } else if (const auto Mem = llvm::dyn_cast<
                  typename InstX86Base<Machine>::Traits::X86OperandMem>(Src)) {
     Mem->emitSegmentOverride(Asm);
-    (Asm->*(Emitter.RegAddr))(DispatchTy, DestReg, Mem->toAsmAddress(Asm));
+    (Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy, Mem->toAsmAddress(Asm));
   } else {
     llvm_unreachable("Unexpected operand type");
   }
 }
 
 template <class Machine, typename DReg_t, typename SReg_t,
           DReg_t (*destEnc)(int32_t), SReg_t (*srcEnc)(int32_t)>
 void emitIASThreeOpImmOps(
     const Cfg *Func, Type DispatchTy, const Variable *Dest, const Operand *Src0,
     const Operand *Src1,
@@ skipping 427 matching lines @@
   case IceType_i16:
     assert(this->getDest()->getRegNum() ==
            InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
     Str << "\tcwtd";
     break;
   case IceType_i32:
     assert(this->getDest()->getRegNum() ==
            InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
     Str << "\tcltd";
     break;
+  case IceType_i64:
+    assert(this->getDest()->getRegNum() ==
+           InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
+    Str << "\tcdto";
+    break;
   }
 }
 
 template <class Machine>
 void InstX86Cbwdq<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 1);
   Operand *Src0 = this->getSrc(0);
   assert(llvm::isa<Variable>(Src0));
@@ skipping 11 matching lines @@
   case IceType_i16:
     assert(this->getDest()->getRegNum() ==
            InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
     Asm->cwd();
     break;
   case IceType_i32:
     assert(this->getDest()->getRegNum() ==
            InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
     Asm->cdq();
     break;
+  case IceType_i64:
+    assert(this->getDest()->getRegNum() ==
+           InstX86Base<Machine>::Traits::RegisterSet::Reg_edx);
+    Asm->cqo();
+    break;
   }
 }
 
 template <class Machine> void InstX86Mul<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 2);
   assert(llvm::isa<Variable>(this->getSrc(0)));
   assert(llvm::cast<Variable>(this->getSrc(0))->getRegNum() ==
@@ skipping 142 matching lines @@
   Dest->emit(Func);
 }
 
 template <class Machine>
 void InstX86Cmov<Machine>::emitIAS(const Cfg *Func) const {
   assert(Condition != InstX86Base<Machine>::Traits::Cond::Br_None);
   assert(this->getDest()->hasReg());
   assert(this->getSrcSize() == 2);
   Operand *Src = this->getSrc(1);
   Type SrcTy = Src->getType();
-  assert(SrcTy == IceType_i16 || SrcTy == IceType_i32);
+  assert(SrcTy == IceType_i16 || SrcTy == IceType_i32 ||
+         (InstX86Base<Machine>::Traits::Is64Bit));
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     if (SrcVar->hasReg()) {
       Asm->cmov(SrcTy, Condition,
                 InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
                     this->getDest()->getRegNum()),
                 InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
                     SrcVar->getRegNum()));
     } else {
@@ skipping 201 matching lines @@
 template <class Machine>
 void InstX86Cvt<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 1);
   const Variable *Dest = this->getDest();
   const Operand *Src = this->getSrc(0);
   Type DestTy = Dest->getType();
   Type SrcTy = Src->getType();
   switch (Variant) {
   case Si2ss: {
     assert(isScalarIntegerType(SrcTy));
-    assert(typeWidthInBytes(SrcTy) <= 4);
+    if (!InstX86Base<Machine>::Traits::Is64Bit) {
+      assert(typeWidthInBytes(SrcTy) <= 4);
+    } else {
+      assert(SrcTy == IceType_i32 || SrcTy == IceType_i64);
+    }
     assert(isScalarFloatingType(DestTy));
     static const typename InstX86Base<Machine>::Traits::Assembler::
         template CastEmitterRegOp<
             typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
             typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister>
             Emitter = {&InstX86Base<Machine>::Traits::Assembler::cvtsi2ss,
                        &InstX86Base<Machine>::Traits::Assembler::cvtsi2ss};
     emitIASCastRegOp<
         Machine,
         typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
         typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
         InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm,
         InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR>(
-        Func, DestTy, Dest, Src, Emitter);
+        Func, DestTy, Dest, SrcTy, Src, Emitter);
     return;
   }
   case Tss2si: {
     assert(isScalarFloatingType(SrcTy));
     assert(isScalarIntegerType(DestTy));
-    assert(typeWidthInBytes(DestTy) <= 4);
+    if (!InstX86Base<Machine>::Traits::Is64Bit) {
+      assert(typeWidthInBytes(DestTy) <= 4);
+    } else {
+      assert(DestTy == IceType_i32 || DestTy == IceType_i64);
+    }
     static const typename InstX86Base<Machine>::Traits::Assembler::
         template CastEmitterRegOp<
             typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
             typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister>
             Emitter = {&InstX86Base<Machine>::Traits::Assembler::cvttss2si,
                        &InstX86Base<Machine>::Traits::Assembler::cvttss2si};
     emitIASCastRegOp<
         Machine,
         typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
         typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
         InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR,
         InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm>(
-        Func, SrcTy, Dest, Src, Emitter);
+        Func, DestTy, Dest, SrcTy, Src, Emitter);
     return;
   }
   case Float2float: {
     assert(isScalarFloatingType(SrcTy));
     assert(isScalarFloatingType(DestTy));
     assert(DestTy != SrcTy);
     static const typename InstX86Base<
         Machine>::Traits::Assembler::XmmEmitterRegOp Emitter = {
         &InstX86Base<Machine>::Traits::Assembler::cvtfloat2float,
         &InstX86Base<Machine>::Traits::Assembler::cvtfloat2float};
@@ skipping 376 matching lines @@
     // lea on x86-32 doesn't accept mem128 operands, so cast VSrc0 to an
     // acceptable type.
     Src0Var->asType(isVectorType(Ty) ? IceType_i32 : Ty)->emit(Func);
   } else {
     Src0->emit(Func);
   }
   Str << ", ";
   this->getDest()->emit(Func);
 }
 
+inline bool isIntegerConstant(const Operand *Op) {
+  return llvm::dyn_cast<ConstantInteger32>(Op) != nullptr ||

[Jim Stichnoth, 2015/08/10 16:08:04]

Use isa<> instead of dyn_cast<> .

[John, 2015/08/10 20:41:17]

Done.

+         llvm::dyn_cast<ConstantInteger64>(Op) != nullptr;
+}
+
 template <class Machine> void InstX86Mov<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 1);
   Operand *Src = this->getSrc(0);
   Type SrcTy = Src->getType();
   Type DestTy = this->getDest()->getType();
-  Str << "\tmov"
-      << (!isScalarFloatingType(DestTy)
-              ? this->getWidthString(SrcTy)
-              : InstX86Base<Machine>::Traits::TypeAttributes[DestTy].SdSsString)
-      << "\t";
+  if (InstX86Base<Machine>::Traits::Is64Bit && DestTy == IceType_i64 &&
+      isIntegerConstant(Src)) {
+    Str << "\tmovabs\t";
+  } else {
+    Str << "\tmov"
+        << (!isScalarFloatingType(DestTy)
+                ? this->getWidthString(SrcTy)
+                : InstX86Base<Machine>::Traits::TypeAttributes[DestTy]
+                      .SdSsString) << "\t";
+  }
   // For an integer truncation operation, src is wider than dest.
   // Ideally, we use a mov instruction whose data width matches the
   // narrower dest.  This is a problem if e.g. src is a register like
   // esi or si where there is no 8-bit version of the register.  To be
   // safe, we instead widen the dest to match src.  This works even
   // for stack-allocated dest variables because typeWidthOnStack()
   // pads to a 4-byte boundary even if only a lower portion is used.
   // TODO: This assert disallows usages such as copying a floating point
   // value between a vector and a scalar (which movss is used for).
   // Clean this up.
@@ skipping 43 matching lines @@
       Func->getTarget()->typeWidthInBytesOnStack(this->getDest()->getType()) ==
       Func->getTarget()->typeWidthInBytesOnStack(Src->getType()));
   if (Dest->hasReg()) {
     if (isScalarFloatingType(DestTy)) {
       emitIASRegOpTyXMM<Machine>(Func, DestTy, Dest, Src, XmmRegEmitter);
       return;
     } else {
       assert(isScalarIntegerType(DestTy));
       // Widen DestTy for truncation (see above note). We should only do this
       // when both Src and Dest are integer types.
+      if (InstX86Base<Machine>::Traits::Is64Bit && DestTy == IceType_i64 &&
+          isIntegerConstant(Src)) {
+        uint64_t value = -1;
+        if (const auto *C64 = llvm::dyn_cast<ConstantInteger64>(Src)) {
+          value = C64->getValue();
+        } else {
+          const auto *C32 = llvm::dyn_cast<ConstantInteger32>(Src);

[Jim Stichnoth, 2015/08/10 16:08:04]

Can probably use llvm::cast<> which would do the assert for you.

[John, 2015/08/10 20:41:17]

Done.

+          assert(C32 != nullptr);
+          value = C32->getValue();
+        }
+        Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>()
+            ->movabs(InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
+                         Dest->getRegNum()),
+                     value);
+        return;
+      }
       if (isScalarIntegerType(SrcTy)) {
         DestTy = SrcTy;
       }
       emitIASRegOpTyGPR<Machine>(Func, DestTy, Dest, Src, GPRRegEmitter);
       return;
     }
   } else {
     // Dest must be Stack and Src *could* be a register. Use Src's type
     // to decide on the emitters.
     typename InstX86Base<Machine>::Traits::Address StackAddr(
@@ skipping 23 matching lines @@
 
 template <class Machine>
 void InstX86Movd<Machine>::emitIAS(const Cfg *Func) const {
   typename InstX86Base<Machine>::Traits::Assembler *Asm =
       Func->getAssembler<typename InstX86Base<Machine>::Traits::Assembler>();
   assert(this->getSrcSize() == 1);
   const Variable *Dest = this->getDest();
   const auto SrcVar = llvm::cast<Variable>(this->getSrc(0));
   // For insert/extract element (one of Src/Dest is an Xmm vector and
   // the other is an int type).
-  if (SrcVar->getType() == IceType_i32) {
-    assert(isVectorType(Dest->getType()));
+  if (SrcVar->getType() == IceType_i32 ||
+      (InstX86Base<Machine>::Traits::Is64Bit &&
+       SrcVar->getType() == IceType_i64)) {
+    assert(isVectorType(Dest->getType()) ||
+           (isScalarFloatingType(Dest->getType()) &&
+            typeWidthInBytes(SrcVar->getType()) ==
+                typeWidthInBytes(Dest->getType())));
     assert(Dest->hasReg());
     typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister DestReg =
         InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
             Dest->getRegNum());
     if (SrcVar->hasReg()) {
-      Asm->movd(DestReg,
+      Asm->movd(SrcVar->getType(), DestReg,
                 InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
                     SrcVar->getRegNum()));
     } else {
       typename InstX86Base<Machine>::Traits::Address StackAddr(
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
               Func->getTarget())
               ->stackVarToAsmOperand(SrcVar));
-      Asm->movd(DestReg, StackAddr);
+      Asm->movd(SrcVar->getType(), DestReg, StackAddr);
     }
   } else {
-    assert(isVectorType(SrcVar->getType()));
+    assert(isVectorType(SrcVar->getType()) ||
+           (isScalarFloatingType(SrcVar->getType()) &&
+            typeWidthInBytes(SrcVar->getType()) ==
+                typeWidthInBytes(Dest->getType())));
     assert(SrcVar->hasReg());
-    assert(Dest->getType() == IceType_i32);
+    assert(Dest->getType() == IceType_i32 ||
+           (InstX86Base<Machine>::Traits::Is64Bit &&
+            Dest->getType() == IceType_i64));
     typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister SrcReg =
         InstX86Base<Machine>::Traits::RegisterSet::getEncodedXmm(
             SrcVar->getRegNum());
     if (Dest->hasReg()) {
-      Asm->movd(InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
+      Asm->movd(Dest->getType(),
+                InstX86Base<Machine>::Traits::RegisterSet::getEncodedGPR(
                     Dest->getRegNum()),
                 SrcReg);
     } else {
       typename InstX86Base<Machine>::Traits::Address StackAddr(
           static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
               Func->getTarget())
               ->stackVarToAsmOperand(Dest));
-      Asm->movd(StackAddr, SrcReg);
+      Asm->movd(Dest->getType(), StackAddr, SrcReg);
     }
   }
 }
 
 template <class Machine>
 void InstX86Movp<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   // TODO(wala,stichnot): movups works with all vector operands, but
   // there exist other instructions (movaps, movdqa, movdqu) that may
@@ skipping 756 matching lines @@
   Type Ty = this->getSrc(0)->getType();
   Str << "xchg." << Ty << " ";
   this->dumpSources(Func);
 }
 
 } // end of namespace X86Internal
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTX86BASEIMPL_H