Subzero. Native 64-bit int arithmetic on x86-64.

src/IceAssemblerX86Base.h

 //===- subzero/src/IceAssemblerX86Base.h - base x86 assembler -*- C++ -*---===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 225 matching lines @@
       Type, typename Traits::XmmRegister, const Immediate &);
 
   struct XmmEmitterShiftOp {
     TypedEmitXmmXmm XmmXmm;
     TypedEmitXmmAddr XmmAddr;
     TypedEmitXmmImm XmmImm;
   };
 
   // Cross Xmm/GPR cast instructions.
   template <typename DReg_t, typename SReg_t> struct CastEmitterRegOp {
-    typedef void (AssemblerX86Base::*TypedEmitRegs)(Type, DReg_t, SReg_t);
+    typedef void (AssemblerX86Base::*TypedEmitRegs)(Type, DReg_t, Type, SReg_t);
     typedef void (AssemblerX86Base::*TypedEmitAddr)(
-        Type, DReg_t, const typename Traits::Address &);
+        Type, DReg_t, Type, const typename Traits::Address &);
 
     TypedEmitRegs RegReg;
     TypedEmitAddr RegAddr;
   };
 
   // Three operand (potentially) cross Xmm/GPR instructions.
   // The last operand must be an immediate.
   template <typename DReg_t, typename SReg_t> struct ThreeOpImmEmitter {
     typedef void (AssemblerX86Base::*TypedEmitRegRegImm)(Type, DReg_t, SReg_t,
                                                          const Immediate &);
@@ skipping 33 matching lines @@
 
   void mov(Type Ty, typename Traits::GPRRegister dst, const Immediate &src);
   void mov(Type Ty, typename Traits::GPRRegister dst,
            typename Traits::GPRRegister src);
   void mov(Type Ty, typename Traits::GPRRegister dst,
            const typename Traits::Address &src);
   void mov(Type Ty, const typename Traits::Address &dst,
            typename Traits::GPRRegister src);
   void mov(Type Ty, const typename Traits::Address &dst, const Immediate &imm);
 
-  void movFromAh(const typename Traits::GPRRegister dst);
+  template <typename T = Traits>
+  typename std::enable_if<T::Is64Bit, void>::type
+  movabs(const typename Traits::GPRRegister Dst, uint64_t Imm64);
+  template <typename T = Traits>
+  typename std::enable_if<!T::Is64Bit, void>::type
+  movabs(const typename Traits::GPRRegister, uint64_t) {
+    llvm::report_fatal_error("movabs is only supported in 64-bit x86 targets.");
+  }
 
   void movzx(Type Ty, typename Traits::GPRRegister dst,
              typename Traits::GPRRegister src);
   void movzx(Type Ty, typename Traits::GPRRegister dst,
              const typename Traits::Address &src);
   void movsx(Type Ty, typename Traits::GPRRegister dst,
              typename Traits::GPRRegister src);
   void movsx(Type Ty, typename Traits::GPRRegister dst,
              const typename Traits::Address &src);
 
   void lea(Type Ty, typename Traits::GPRRegister dst,
            const typename Traits::Address &src);
 
   void cmov(Type Ty, typename Traits::Cond::BrCond cond,
             typename Traits::GPRRegister dst, typename Traits::GPRRegister src);
   void cmov(Type Ty, typename Traits::Cond::BrCond cond,
             typename Traits::GPRRegister dst,
             const typename Traits::Address &src);
 
   void rep_movsb();
 
   void movss(Type Ty, typename Traits::XmmRegister dst,
              const typename Traits::Address &src);
   void movss(Type Ty, const typename Traits::Address &dst,
              typename Traits::XmmRegister src);
   void movss(Type Ty, typename Traits::XmmRegister dst,
              typename Traits::XmmRegister src);
 
-  void movd(typename Traits::XmmRegister dst, typename Traits::GPRRegister src);
-  void movd(typename Traits::XmmRegister dst,
+  void movd(Type SrcTy, typename Traits::XmmRegister dst,
+            typename Traits::GPRRegister src);
+  void movd(Type SrcTy, typename Traits::XmmRegister dst,
             const typename Traits::Address &src);
-  void movd(typename Traits::GPRRegister dst, typename Traits::XmmRegister src);
-  void movd(const typename Traits::Address &dst,
+  void movd(Type DestTy, typename Traits::GPRRegister dst,
+            typename Traits::XmmRegister src);
+  void movd(Type DestTy, const typename Traits::Address &dst,
             typename Traits::XmmRegister src);
 
   void movq(typename Traits::XmmRegister dst, typename Traits::XmmRegister src);
   void movq(const typename Traits::Address &dst,
             typename Traits::XmmRegister src);
   void movq(typename Traits::XmmRegister dst,
             const typename Traits::Address &src);
 
   void addss(Type Ty, typename Traits::XmmRegister dst,
              typename Traits::XmmRegister src);
@@ skipping 151 matching lines @@
   void cvtdq2ps(Type, typename Traits::XmmRegister dst,
                 typename Traits::XmmRegister src);
   void cvtdq2ps(Type, typename Traits::XmmRegister dst,
                 const typename Traits::Address &src);
 
   void cvttps2dq(Type, typename Traits::XmmRegister dst,
                  typename Traits::XmmRegister src);
   void cvttps2dq(Type, typename Traits::XmmRegister dst,
                  const typename Traits::Address &src);
 
-  void cvtsi2ss(Type DestTy, typename Traits::XmmRegister dst,
+  void cvtsi2ss(Type DestTy, typename Traits::XmmRegister dst, Type SrcTy,
                 typename Traits::GPRRegister src);
-  void cvtsi2ss(Type DestTy, typename Traits::XmmRegister dst,
+  void cvtsi2ss(Type DestTy, typename Traits::XmmRegister dst, Type SrcTy,
                 const typename Traits::Address &src);
 
   void cvtfloat2float(Type SrcTy, typename Traits::XmmRegister dst,
                       typename Traits::XmmRegister src);
   void cvtfloat2float(Type SrcTy, typename Traits::XmmRegister dst,
                       const typename Traits::Address &src);
 
-  void cvttss2si(Type SrcTy, typename Traits::GPRRegister dst,
+  void cvttss2si(Type DestTy, typename Traits::GPRRegister dst, Type SrcTy,
                  typename Traits::XmmRegister src);
-  void cvttss2si(Type SrcTy, typename Traits::GPRRegister dst,
+  void cvttss2si(Type DestTy, typename Traits::GPRRegister dst, Type SrcTy,
                  const typename Traits::Address &src);
 
   void ucomiss(Type Ty, typename Traits::XmmRegister a,
                typename Traits::XmmRegister b);
   void ucomiss(Type Ty, typename Traits::XmmRegister a,
                const typename Traits::Address &b);
 
   void movmskpd(typename Traits::GPRRegister dst,
                 typename Traits::XmmRegister src);
   void movmskps(typename Traits::GPRRegister dst,
@@ skipping 182 matching lines @@
            const typename Traits::Address &address);
   void sbb(Type Ty, typename Traits::GPRRegister reg, const Immediate &imm);
   void sbb(Type Ty, const typename Traits::Address &address,
            typename Traits::GPRRegister reg);
   void sbb(Type Ty, const typename Traits::Address &address,
            const Immediate &imm);
 
   void cbw();
   void cwd();
   void cdq();
+  template <typename T = Traits>
+  typename std::enable_if<T::Is64Bit, void>::type cqo();
+  template <typename T = Traits>
+  typename std::enable_if<!T::Is64Bit, void>::type cqo() {
+    llvm::report_fatal_error("CQO is only available in 64-bit x86 backends.");
+  }
 
   void div(Type Ty, typename Traits::GPRRegister reg);
   void div(Type Ty, const typename Traits::Address &address);
 
   void idiv(Type Ty, typename Traits::GPRRegister reg);
   void idiv(Type Ty, const typename Traits::Address &address);
 
   void imul(Type Ty, typename Traits::GPRRegister dst,
             typename Traits::GPRRegister src);
   void imul(Type Ty, typename Traits::GPRRegister reg, const Immediate &imm);
@@ skipping 191 matching lines @@
 
   template <typename RegType>
   bool is8BitRegisterRequiringRex(const Type Ty, const RegType Reg) {
     static constexpr bool IsGPR =
         std::is_same<typename std::decay<RegType>::type,
                      typename Traits::ByteRegister>::value ||
         std::is_same<typename std::decay<RegType>::type,
                      typename Traits::GPRRegister>::value;
 
     return IsGPR && (Reg & 0x04) != 0 && (Reg & 0x08) == 0 &&
-           isByteSizedArithType(Ty);
+           isByteSizedType(Ty);
   };
 
   // assembleAndEmitRex is used for determining which (if any) rex prefix should
   // be emitted for the current instruction. It allows different types for Reg
   // and Rm because they could be of different types (e.g., in mov[sz]x
   // instrutions.) If Addr is not nullptr, then Rm is ignored, and Rex.B is
   // determined by Addr instead. TyRm is still used to determine Addr's size.
   template <typename RegType, typename RmType, typename T = Traits>
   typename std::enable_if<T::Is64Bit, void>::type
   assembleAndEmitRex(const Type TyReg, const RegType Reg, const Type TyRm,
@@ skipping 95 matching lines @@
   emitUint8(0x66);
 }
 
 } // end of namespace X86Internal
 
 } // end of namespace Ice
 
 #include "IceAssemblerX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICEASSEMBLERX86BASE_H