Subzero. Native 64-bit int arithmetic on x86-64.

src/IceTargetLoweringX8664Traits.h

 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 48 matching lines @@
 
   using GPRRegister = ::Ice::RegX8664::GPRRegister;
   using XmmRegister = ::Ice::RegX8664::XmmRegister;
   using ByteRegister = ::Ice::RegX8664::ByteRegister;
 
   using Cond = ::Ice::CondX8664;
 
   using RegisterSet = ::Ice::RegX8664;
   static const GPRRegister Encoded_Reg_Accumulator = RegX8664::Encoded_Reg_eax;
   static const GPRRegister Encoded_Reg_Counter = RegX8664::Encoded_Reg_ecx;
-  static const FixupKind PcRelFixup = llvm::ELF::R_386_PC32; // TODO(jpp): ???
+  static const FixupKind PcRelFixup = llvm::ELF::R_X86_64_PC32;
+  static const FixupKind RelFixup = llvm::ELF::R_X86_64_32S;
 
   class Operand {
   public:
     enum RexBits {
       RexNone = 0x00,
       RexBase = 0x40,
       RexW = RexBase | (1 << 3),
       RexR = RexBase | (1 << 2),
       RexX = RexBase | (1 << 1),
       RexB = RexBase | (1 << 0),
@@ skipping 183 matching lines @@
       SetFixup(Fixup);
     }
 
     // TODO(jpp): remove this.
     static Address Absolute(RelocOffsetT Offset, AssemblerFixup *Fixup) {
       return Address(ABSOLUTE, Offset, Fixup);
     }
 
     static Address ofConstPool(Assembler *Asm, const Constant *Imm) {
       // TODO(jpp): ???
-      AssemblerFixup *Fixup = Asm->createFixup(llvm::ELF::R_386_32, Imm);
-      const RelocOffsetT Offset = 0;
+      AssemblerFixup *Fixup = Asm->createFixup(RelFixup, Imm);
+      const RelocOffsetT Offset = 4;
       return Address(ABSOLUTE, Offset, Fixup);
     }
   };
 
   //----------------------------------------------------------------------------
   //     __      ______  __     __  ______  ______  __  __   __  ______
   //    /\ \    /\  __ \/\ \  _ \ \/\  ___\/\  == \/\ \/\ "-.\ \/\  ___\
   //    \ \ \___\ \ \/\ \ \ \/ ".\ \ \  __\\ \  __<\ \ \ \ \-.  \ \ \__ \
   //     \ \_____\ \_____\ \__/".~\_\ \_____\ \_\ \_\ \_\ \_\\"\_\ \_____\
   //      \/_____/\/_____/\/_/   \/_/\/_____/\/_/ /_/\/_/\/_/ \/_/\/_____/
   //
   //----------------------------------------------------------------------------
   enum InstructionSet {
     Begin,
     // SSE2 is the PNaCl baseline instruction set.
     SSE2 = Begin,
     SSE4_1,
     End
   };
 
   static const char *TargetName;
+  static constexpr Type WordType = IceType_i64;
 
   static IceString getRegName(SizeT RegNum, Type Ty) {
     assert(RegNum < RegisterSet::Reg_NUM);
     static const struct {
       const char *const Name8;
       const char *const Name16;
       const char *const Name /*32*/;
       const char *const Name64;
     } RegNames[] = {
 #define X(val, encode, name64, name32, name16, name8, scratch, preserved,      \
@@ skipping 18 matching lines @@
   }
 
   static void initRegisterSet(llvm::SmallBitVector *IntegerRegisters,
                               llvm::SmallBitVector *IntegerRegistersI8,
                               llvm::SmallBitVector *FloatRegisters,
                               llvm::SmallBitVector *VectorRegisters,
                               llvm::SmallBitVector *ScratchRegs) {
 #define X(val, encode, name64, name32, name16, name8, scratch, preserved,      \
           stackptr, frameptr, isInt, isFP)                                     \
   (*IntegerRegisters)[RegisterSet::val] = isInt;                               \
-  (*IntegerRegistersI8)[RegisterSet::val] = 1;                                 \
+  (*IntegerRegistersI8)[RegisterSet::val] = isInt;                             \
   (*FloatRegisters)[RegisterSet::val] = isFP;                                  \
   (*VectorRegisters)[RegisterSet::val] = isFP;                                 \
   (*ScratchRegs)[RegisterSet::val] = scratch;
     REGX8664_TABLE;
 #undef X
   }
 
   static llvm::SmallBitVector
   getRegisterSet(TargetLowering::RegSetMask Include,
                  TargetLowering::RegSetMask Exclude) {
@@ skipping 98 matching lines @@
   /// The maximum number of arguments to pass in GPR registers
   static const uint32_t X86_MAX_GPR_ARGS = 6;
   /// The number of bits in a byte
   static const uint32_t X86_CHAR_BIT = 8;
   /// Stack alignment. This is defined in IceTargetLoweringX8664.cpp because it
   /// is used as an argument to std::max(), and the default std::less<T> has an
   /// operator(T const&, T const&) which requires this member to have an
   /// address.
   static const uint32_t X86_STACK_ALIGNMENT_BYTES;
   /// Size of the return address on the stack
-  static const uint32_t X86_RET_IP_SIZE_BYTES = 4;
+  static const uint32_t X86_RET_IP_SIZE_BYTES = 8;
   /// The number of different NOP instructions
   static const uint32_t X86_NUM_NOP_VARIANTS = 5;
 
   /// Value is in bytes. Return Value adjusted to the next highest multiple
   /// of the stack alignment.
   static uint32_t applyStackAlignment(uint32_t Value) {
     return Utils::applyAlignment(Value, X86_STACK_ALIGNMENT_BYTES);
   }
 
   /// Return the type which the elements of the vector have in the X86
@@ skipping 245 matching lines @@
 
 } // end of namespace X86Internal
 
 namespace X8664 {
 using Traits = ::Ice::X86Internal::MachineTraits<TargetX8664>;
 } // end of namespace X8664
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H