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Side by Side Diff: runtime/vm/assembler_arm.cc

Issue 12726011: Enables cross-compilation of the VM for ARM. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 8 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" 5 #include "vm/globals.h"
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/simulator.h" 9 #include "vm/simulator.h"
10 #include "vm/runtime_entry.h" 10 #include "vm/runtime_entry.h"
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33 } 33 }
34 #endif 34 #endif
35 35
36 36
37 #define __ assembler. 37 #define __ assembler.
38 38
39 void CPUFeatures::InitOnce() { 39 void CPUFeatures::InitOnce() {
40 #if defined(USING_SIMULATOR) 40 #if defined(USING_SIMULATOR)
41 integer_division_supported_ = true; 41 integer_division_supported_ = true;
42 #else 42 #else
43 Assembler assembler; 43 integer_division_supported_ = false;
44 __ mrc(R0, 15, 0, 0, 2, 0);
45 __ Lsr(R0, R0, 24);
46 __ and_(R0, R0, ShifterOperand(0xf));
47 __ Ret();
48
49 const Code& code =
50 Code::Handle(Code::FinalizeCode("DetectCPUFeatures", &assembler));
51 Instructions& instructions = Instructions::Handle(code.instructions());
52 typedef int32_t (*DetectCPUFeatures)();
53 int32_t features =
54 reinterpret_cast<DetectCPUFeatures>(instructions.EntryPoint())();
55 integer_division_supported_ = features != 0;
56 #endif // defined(USING_SIMULATOR) 44 #endif // defined(USING_SIMULATOR)
57 #if defined(DEBUG) 45 #if defined(DEBUG)
58 initialized_ = true; 46 initialized_ = true;
59 #endif 47 #endif
60 } 48 }
61 49
62 #undef __ 50 #undef __
63 51
64 52
65 // Instruction encoding bits. 53 // Instruction encoding bits.
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2126 2114
2127 const char* Assembler::FpuRegisterName(FpuRegister reg) { 2115 const char* Assembler::FpuRegisterName(FpuRegister reg) {
2128 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); 2116 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
2129 return fpu_reg_names[reg]; 2117 return fpu_reg_names[reg];
2130 } 2118 }
2131 2119
2132 } // namespace dart 2120 } // namespace dart
2133 2121
2134 #endif // defined TARGET_ARCH_ARM 2122 #endif // defined TARGET_ARCH_ARM
2135 2123
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