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| 1 //===- subzero/src/IceCfgNode.cpp - Basic block (node) implementation -----===// | 1 //===- subzero/src/IceCfgNode.cpp - Basic block (node) implementation -----===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 573 // Guess that the number of live ranges beginning is roughly the | 573 // Guess that the number of live ranges beginning is roughly the |
| 574 // number of instructions, and same for live ranges ending. | 574 // number of instructions, and same for live ranges ending. |
| 575 LiveBegin->reserve(getInstCountEstimate()); | 575 LiveBegin->reserve(getInstCountEstimate()); |
| 576 LiveEnd->reserve(getInstCountEstimate()); | 576 LiveEnd->reserve(getInstCountEstimate()); |
| 577 } | 577 } |
| 578 // Initialize Live to be the union of all successors' LiveIn. | 578 // Initialize Live to be the union of all successors' LiveIn. |
| 579 for (CfgNode *Succ : OutEdges) { | 579 for (CfgNode *Succ : OutEdges) { |
| 580 Live |= Liveness->getLiveIn(Succ); | 580 Live |= Liveness->getLiveIn(Succ); |
| 581 // Mark corresponding argument of phis in successor as live. | 581 // Mark corresponding argument of phis in successor as live. |
| 582 for (Inst &I : Succ->Phis) { | 582 for (Inst &I : Succ->Phis) { |
| 583 if (I.isDeleted()) |
| 584 continue; |
| 583 auto Phi = llvm::dyn_cast<InstPhi>(&I); | 585 auto Phi = llvm::dyn_cast<InstPhi>(&I); |
| 584 Phi->livenessPhiOperand(Live, this, Liveness); | 586 Phi->livenessPhiOperand(Live, this, Liveness); |
| 585 } | 587 } |
| 586 } | 588 } |
| 587 Liveness->getLiveOut(this) = Live; | 589 Liveness->getLiveOut(this) = Live; |
| 588 | 590 |
| 589 // Process regular instructions in reverse order. | 591 // Process regular instructions in reverse order. |
| 590 for (Inst &I : reverse_range(Insts)) { | 592 for (Inst &I : reverse_range(Insts)) { |
| 591 if (I.isDeleted()) | 593 if (I.isDeleted()) |
| 592 continue; | 594 continue; |
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| 691 // the Variable's live range begins and ends in this block. If | 693 // the Variable's live range begins and ends in this block. If |
| 692 // i1<i2, then i1's live range begins at instruction IBB->second | 694 // i1<i2, then i1's live range begins at instruction IBB->second |
| 693 // and extends through the end of the block. If i1>i2, then i2's | 695 // and extends through the end of the block. If i1>i2, then i2's |
| 694 // live range begins at the first instruction of the block and | 696 // live range begins at the first instruction of the block and |
| 695 // ends at IEB->second. In any case, we choose the lesser of i1 | 697 // ends at IEB->second. In any case, we choose the lesser of i1 |
| 696 // and i2 and proceed accordingly. | 698 // and i2 and proceed accordingly. |
| 697 InstNumberT LB = i == i1 ? IBB->second : FirstInstNum; | 699 InstNumberT LB = i == i1 ? IBB->second : FirstInstNum; |
| 698 InstNumberT LE = i == i2 ? IEB->second : LastInstNum + 1; | 700 InstNumberT LE = i == i2 ? IEB->second : LastInstNum + 1; |
| 699 | 701 |
| 700 Variable *Var = Liveness->getVariable(i, this); | 702 Variable *Var = Liveness->getVariable(i, this); |
| 703 // TODO(stichnot): Push getIgnoreLiveness() into the initialization of |
| 704 // Liveness::RangeMask so that LiveBegin and LiveEnd never even reference |
| 705 // such variables. |
| 701 if (!Var->getIgnoreLiveness()) { | 706 if (!Var->getIgnoreLiveness()) { |
| 702 if (LB > LE) { | 707 if (LB > LE) { |
| 703 Var->addLiveRange(FirstInstNum, LE, 1); | 708 Var->addLiveRange(FirstInstNum, LE, 1); |
| 704 Var->addLiveRange(LB, LastInstNum + 1, 1); | 709 Var->addLiveRange(LB, LastInstNum + 1, 1); |
| 705 // Assert that Var is a global variable by checking that its | 710 // Assert that Var is a global variable by checking that its |
| 706 // liveness index is less than the number of globals. This | 711 // liveness index is less than the number of globals. This |
| 707 // ensures that the LiveInAndOut[] access is valid. | 712 // ensures that the LiveInAndOut[] access is valid. |
| 708 assert(i < Liveness->getNumGlobalVars()); | 713 assert(i < Liveness->getNumGlobalVars()); |
| 709 LiveInAndOut[i] = false; | 714 LiveInAndOut[i] = false; |
| 710 } else { | 715 } else { |
| 711 Var->addLiveRange(LB, LE, 1); | 716 Var->addLiveRange(LB, LE, 1); |
| 712 } | 717 } |
| 713 } | 718 } |
| 714 if (i == i1) | 719 if (i == i1) |
| 715 ++IBB; | 720 ++IBB; |
| 716 if (i == i2) | 721 if (i == i2) |
| 717 ++IEB; | 722 ++IEB; |
| 718 } | 723 } |
| 719 // Process the variables that are live across the entire block. | 724 // Process the variables that are live across the entire block. |
| 720 for (int i = LiveInAndOut.find_first(); i != -1; | 725 for (int i = LiveInAndOut.find_first(); i != -1; |
| 721 i = LiveInAndOut.find_next(i)) { | 726 i = LiveInAndOut.find_next(i)) { |
| 722 Variable *Var = Liveness->getVariable(i, this); | 727 Variable *Var = Liveness->getVariable(i, this); |
| 723 Var->addLiveRange(FirstInstNum, LastInstNum + 1, 1); | 728 if (Liveness->getRangeMask(Var->getIndex())) |
| 729 Var->addLiveRange(FirstInstNum, LastInstNum + 1, 1); |
| 724 } | 730 } |
| 725 } | 731 } |
| 726 | 732 |
| 727 // If this node contains only deleted instructions, and ends in an | 733 // If this node contains only deleted instructions, and ends in an |
| 728 // unconditional branch, contract the node by repointing all its | 734 // unconditional branch, contract the node by repointing all its |
| 729 // in-edges to its successor. | 735 // in-edges to its successor. |
| 730 void CfgNode::contractIfEmpty() { | 736 void CfgNode::contractIfEmpty() { |
| 731 if (InEdges.empty()) | 737 if (InEdges.empty()) |
| 732 return; | 738 return; |
| 733 Inst *Branch = nullptr; | 739 Inst *Branch = nullptr; |
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| 1277 InstIntrinsicCall *Inst = InstIntrinsicCall::create( | 1283 InstIntrinsicCall *Inst = InstIntrinsicCall::create( |
| 1278 Func, 5, Func->makeVariable(IceType_i64), RMWI64Name, Info->Info); | 1284 Func, 5, Func->makeVariable(IceType_i64), RMWI64Name, Info->Info); |
| 1279 Inst->addArg(AtomicRMWOp); | 1285 Inst->addArg(AtomicRMWOp); |
| 1280 Inst->addArg(Counter); | 1286 Inst->addArg(Counter); |
| 1281 Inst->addArg(One); | 1287 Inst->addArg(One); |
| 1282 Inst->addArg(OrderAcquireRelease); | 1288 Inst->addArg(OrderAcquireRelease); |
| 1283 Insts.push_front(Inst); | 1289 Insts.push_front(Inst); |
| 1284 } | 1290 } |
| 1285 | 1291 |
| 1286 } // end of namespace Ice | 1292 } // end of namespace Ice |
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