Index: src/trusted/validator_ragel/unreviewed/parse_instruction.rl |
=================================================================== |
--- src/trusted/validator_ragel/unreviewed/parse_instruction.rl (revision 10997) |
+++ src/trusted/validator_ragel/unreviewed/parse_instruction.rl (working copy) |
@@ -900,40 +900,3 @@ |
action att_show_name_suffix_x { SET_ATT_INSTRUCTION_SUFFIX("x"); } |
action att_show_name_suffix_y { SET_ATT_INSTRUCTION_SUFFIX("y"); } |
}%% |
- |
-%%{ |
- machine decoder; |
- |
- action end_of_instruction_cleanup { |
- process_instruction(instruction_begin, current_position + 1, &instruction, |
- userdata); |
- instruction_begin = current_position + 1; |
- SET_DISP_TYPE(DISPNONE); |
- SET_IMM_TYPE(IMMNONE); |
- SET_IMM2_TYPE(IMMNONE); |
- SET_REX_PREFIX(FALSE); |
- SET_DATA16_PREFIX(FALSE); |
- SET_LOCK_PREFIX(FALSE); |
- SET_REPNZ_PREFIX(FALSE); |
- SET_REPZ_PREFIX(FALSE); |
- SET_BRANCH_NOT_TAKEN(FALSE); |
- SET_BRANCH_TAKEN(FALSE); |
- /* Top three bis of VEX2 are inverted: see AMD/Intel manual. */ |
- SET_VEX_PREFIX2(VEX_R | VEX_X | VEX_B); |
- SET_VEX_PREFIX3(0x00); |
- SET_ATT_INSTRUCTION_SUFFIX(NULL); |
- CLEAR_SPURIOUS_REX_B(); |
- CLEAR_SPURIOUS_REX_X(); |
- CLEAR_SPURIOUS_REX_R(); |
- CLEAR_SPURIOUS_REX_W(); |
- } |
- |
- action report_fatal_error { |
- process_error(current_position, userdata); |
- result = FALSE; |
- goto error_detected; |
- } |
- |
- decoder = (one_instruction @end_of_instruction_cleanup)* |
- $!report_fatal_error; |
-}%% |